24 ADC

ADC Input Select

If a higher-priority ADC channel is triggered during the last 1–2 clock cycles of an active sample window, the ADC input select may switch to the new channel before the current sample is complete. The sample counter may not restart, and the new channel may be acknowledged too early. This can cause an incomplete sample time and produce an incorrect conversion result for the high-priority channel. This issue applies to single-core, multi-core, and interleaved-core ADC modes.

Workaround

Do not trigger a higher-priority ADC channel near the end of another channel’s sampling period. Add enough guard time between triggers based on the configured SAMC sample time. This prevents back-to-back triggers from occurring in the final clock cycles of an active sample window.

Affected Silicon Revisions

A1A2
XX