12 Serial Quad Interface (SQI)

DDR

SQI Dual and Quad mode Double Data Rate (DDR) write modes are inoperative.

Workaround

None.

Affected Silicon Revisions

A1A2
X-

XIP

Byte and half-word transfers are not supported in XIP mode.

Workaround

When using XIP mode, transfer access should be limited to the word size.

Affected Silicon Revisions

A1A2
XX

DMA

When using a DMA descriptor with the Status Polling Option bit set, the PKTCOMPIF interrupt flag will be set before the status check has completed.

Workaround

  • Disable the interrupts for the descriptor that uses status check.
  • Add a new descriptor (preferably read) to the list right after the one with the status check bit set.
  • Set the interrupt enable on this descriptor CBD_INT_EN and PKT_INT_EN.
  • The execution of this descriptor will only happen after the previous one is complete (including its corresponding status check).
  • Use the PKTCOMPIF, which will be set after the whole operation has completed.
Note: Ensure to manually clear PKTCOMPIF when starting a DMA operation.

Affected Silicon Revisions

A1A2
XX