1 Silicon Issue Summary
| Module | Feature | Errata # | Issue Summary | Affected Revisions | |
|---|---|---|---|---|---|
| A1 | A2 | ||||
| AC | CTRLA.SWRST | 2.1.1 | Resisters that are not reset by SWRST can be written before SYNCBUSY.SWRST is cleared. | X | X |
| CAN | Debug Message Status Register | 2.2.1 | The CAN register field RXF1S.DMS is not cleared by setting CCCR.CCE. | X | X |
| CAN | Sequential CAN Msg TX | 2.2.2 | Message order inversion when transmitting from dedicated Tx Buffers configured with same Message ID. | X | X |
| DMA | CRC | 2.3.1 | DMA Channel CRCROUT and CRCXOR settings are applied to CRC data only, and not applied on CRC Append Data. | X | X |
| DMA | BYTORD | 2.3.2 | Byte re-ordering settings incorrectly applied to descriptor data. | X | X |
| DMA | Pattern Match | 2.3.3 | Pattern Match feature does not work when channel set to Fixed Word Address Increment | X | X |
| DMA | Linked List Event System Abort | 2.3.4 | Event abort issues in Linked List Operation mode. | X | X |
| DMA | SYNCBUSY.ENABLE | 2.3.5 | SYNCBUSY.ENABLE May Remain Set When Repeatedly Enabling or Disabling SPI/I2C Client Modes | X | X |
| DMA | When CRCEN = 1 output data is broken | 2.3.6 | CRC in fixed read addressing modes is broken (CHCTRLBn.RAS). | X | X |
| DMA | IP Header Checksum Mode | 2.3.7 | CRCMD 7 is not working correctly with ras = 3. | X | X |
| DMA | Event System and Pattern Match Aborts | 2.3.8 | Event System and Pattern Match Aborts Fail to Clear Internal Flag. | X | X |
| DMA | Descriptor Loading | 2.3.9 | CHCTRLA.ENABLE = 1 and LLEN = 1 does load the descriptor. | X | X |
| DMA | Pattern Match | 2.3.10 | DMA event output flag may not clear after pattern match or event abort. | X | X |
| IxS | MCLKn | 2.4.1 | Assigning the IxS MCLKn signal to a pin through the I/O MUX does not enable the output. | X | X |
| IxS | FRMCNT | 2.4.2 | FRAMECTRL.FRMCNT set to 0x0 results in frame sync rate of 2. | X | X |
| IxS | I8S | 2.4.3 |
When operating in I8S left/right justified client mode, data from the client is not transmitted properly and is erroneous. | X | X |
| MCLK | CLKDIV | 2.5.1 | PSLVERR is generated when RSVD values are written to CLKDIV registers. | X | X |
| MCRAMC | FLTCTRL | 2.6.1 | MCRAMC_FLTCTRL.FLTMD field is not write protected when FLTEN = 1 | X | X |
| NVMCTRL | RDBUFWS | 2.7.1 | Setting RDBUFWS = 1 stalls the FCR read accesses. | X | - |
| NVMCTRL | PRM | 2.7.2 | NVMCTRL Power-Reduction mode is non-functional. | X | X |
| NVMCTRL | CRCMLEN | 2.7.3 | CRCMLEN active bits can exceed the PFM size for devices with Flash panels smaller than 8M Bytes. | X | X |
| NVMCTRL | CTRLA.ADRWS | 2.7.4 | When CTRLA.ADRWS is set to 1, reads to the same address across NVM regional boundaries can yield stale data. | X | - |
| NVMCTRL | CRC | 2.7.5 | FCR does not check addresses to verify they fall within a valid Flash memory region. | X | X |
| NVMCTRL | ECCCTRL | 2.7.6 | The ECC mode settings 0x10 and 0x01 are not functional for all possible read/write operations. | X | - |
| NVMCTRL | DBGCTRL.DBGECC | 2.7.7 | Bus errors reported to debugger when FCR -> DBGCTRL.DBGECC = 0 (NOERR). | X | X |
| NVMCTRL | Fault Address Capture | 2.7.8 | When computing CRC on the on-chip Flash and a double ECC error is detected, FFLTCAP.FLTADR does not capture the correct Flash physical address at which a fault occurred. | X | X |
| PORT | WRCONFIG | 2.8.1 | Setting a pad in open drain mode will override other pin functions. | X | X |
| RPMU | BU Sleep Mode | 2.9.1 | Some registers that should persists after an RTC wake-up event from Back-Up Sleep mode are reset to zero. | X | X |
| RPMU | Hibernate Mode | 2.9.2 | RCAUSE.BKUPEXIT.HIB not set on wake up from Hibernate mode, when in Debug mode. | X | X |
| RPMU | RSTC.DBGCTRL | 2.9.3 | The RSTC DBCTRL register should only be reset by debugger reset but is also reset by other reset sources. | X | X |
| SDHC | PSR.CARDINS | 2.10.1 | The card detect status bit and downstream interrupt flag bits are updated only after internal clock is enabled. | X | X |
| SERCOM SPI | CTRLB.MSSEN | 2.11.1 | CTRLB.MSSEN is not useful for hardware control of SS. | X | X |
| SERCOM SPI | I8S | 2.11.2 | When operating in I8S left/right justified, client mode, data from the client is not transmitted properly and is erroneous. | X | X |
| SQI | DDR | 2.12.1 | SQI Dual and Quad mode write modes are inoperable. | X | - |
| SQI | XIP | 2.12.2 | Byte and half-word transfers are not supported in XIP mode. | X | X |
| SQI | DMA | 2.12.3 | When using a DMA descriptor with the status polling option bit set, the PKTCOMPIF interrupt flag will set before the status check has completed. | X | X |
| TCC | DMA Request | 2.13.1 | The DMA One Shot trigger mode does not function in Capture Compare mode. | X | X |
| TCC | RAMP2 | 2.13.2 | In two ramp modes (RAMP2, RAMP2A, RAMP2C, RAMP2CS) counting down mode is not supported. | X | X |
| TCC | RAMP2 Dithering | 2.13.3 | Retrigger in RAMP2 operations is not supported in Dithering mode. | X | X |
| TCC | CC | 2.13.4 | If a Retrigger event (EVCTRL.EVACTn = 0x1, RETRIGGER) occurs exactly at the Channel Compare Match [n] time, the next Waveform Output [n] is corrupted. | X | X |
| TCC | DMA | 2.13.5 | DMA trigger on Channel Compare Match is not functional. | X | X |
| USB | DBG | 2.14.1 | USB INTRUSB, and INTrRx and INTrTx registers are cleared by debug access. | X | X |
| USB | APB | 2.14.2 | Addressing some PHY registers set the APB clock request permanently. | X | X |
| USB | ESD Protection | 2.14.3 | Reduced HBM ESD robustness on VUSB3V3_0 and VUSB3V3_1 supply pads. | X | |
| TRAM | DRP | 2.15.1 | When Data Scrambling is enabled, accessing TRAM during DRP routine can lead to corrupted (read or write) data. | X | X |
| SERCOM | LIN | 2.16.1 | LIN Host mode adds non-conformal delay between break and sync bits. | X | X |
| SERCOM | LIN - Two Stop Bits | 2.16.2 | Two stop bits mode is not supported in SERCOM LIN operation. | X | X |
| SERCOM | SPI Host Mode | 2.16.3 | SERCOM SPI TXC Flag Issue. | X | |
| SERCOM | SPI/I2C Client Mode | 2.16.4 | SYNCBUSY.ENABLE can get stuck if GCLK is slower than APB clock. | X | X |
| SERCOM | I2C Host Mode | 2.16.5 | I2C host clock limitation when using the FIFO. | X | X |
| FREQM | STATUS.BUSY | 2.17.1 | If during measurement slot, the STATUS.BUSY will never de-assert and DONE interrupt will not be raised. | X | X |
| OSCCTRL | DFLL48M | 2.18.1 | When the DFLL48M is used dynamically, tuning can be corrupted when re-enabling. | X | X |
| OSCCTRL | DFLL | 2.18.2 | DFLL Fails to Lock at 8 MHz in Low Power Mode under Extreme Conditions. | X | X |
| SUPC | BOR | 2.19.1 | The SUPC BOR register is reset after a watchdog or system reset. | X | X |
| NMI | GCLK | 2.20.1 | If NMI is configured in synchronous edge detection mode, spurious interrupts may occur after a software reset. | X | X |
| Device | Chip Erase | 2.21.1 | Chip erase is not functional for some parts. | - | X |
| DSU | FPACKAGE-100 | 2.22.1 | Some GPIOs are not acting properly according to FPACKAGE-100 config. | X | X |
| ITM | Serial Wire Output (SWO) | 2.23.1 | SWO pin trace is not working. | X | X |
| ADC | ADC Input Select | 2.24.1 | A higher-priority ADC trigger arriving near the end of an active sample window may cause an incomplete sample and an incorrect conversion result. | X | X |
| TMR | Periodic Daily Event | 2.25.1 | Periodic Daily Event is getting generated at 23:59:58 instead of 23:59:59 in Mode 2. | X | X |
| PM | STANBY SleepWalking Mode | 2.26.1 | Excessive Clock Activity in STANDBY Mode with an Active Host. | X | |
| GPIO | PORT AHB Access | 2.27.1 | Phantom DIR register clear after power cycle when AHB access is implemented. | X | X |
Note:
- Cells with ‘X’ indicate the issue is present in this revision of the silicon
- Cells with ‘-’ indicate this silicon revision does not exist for this issue
- The blank cell indicates the issue has been corrected or does not exist in this revision of the silicon