19.11.14 Output Compare Register 3 B Low and High byte

The OCR3BL and OCR3BH register pair represents the 16-bit value, OCR3B. The low byte [7:0] (suffix L) is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.

Name: OCR3BL and OCR3BH
Offset: 0x9A
Reset: 0x00
Property: -

Bit 15141312111098 
 OCR3B[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 OCR3B[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 15:0 – OCR3B[15:0] Output Compare 3 B

The Output Compare Registers contain a 16-bit value that is continuously compared with the counter value (TCNT3). A match can be used to generate an Output Compare interrupt or to generate a waveform output on the OC3B pin.

The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. Refer to Accessing 16-bit Timer/Counter Registers for details.