19.11.15 TC4 Control Register A
| Name: | TCCR4A |
| Offset: | 0xA0 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COM4A[1:0] | COM4B[1:0] | WGM4[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 4:5, 6:7 – COM4 Compare Output Mode for Channel
The COM4A[1:0] and COM4B[1:0] control the Output Compare pins (OC4A and OC4B respectively) behavior. If one or both of the COM4A[1:0] bits are written to one, the OC4A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM4B[1:0] bit are written to one, the OC4B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC4A or OC4B pin must be set in order to enable the output driver.
When the OC4A or OC4B is connected to the pin, the function of the COM4x[1:0] bits is dependent on the WGM4[3:0] bits setting. The table below shows the COM4n[1:0] bit functionality when the WGM4[3:0] bits are set to a Normal or a CTC mode (non-PWM).
For OC3B or OC4B when not using the Output Compare Modulator, PORTD2 must also be set in order to enable the output.
| COM4A[1]/COM4B[1] | COM4A[0]/COM4B[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC4A/OC4B disconnected. |
| 0 | 1 | Toggle OC4A/OC4B on Compare Match. |
| 1 | 0 | Clear OC4A/OC4B on Compare Match (Set output to low level). |
| 1 | 1 | Set OC4A/OC4B on Compare Match (Set output to high level). |
The table below shows the COM4x[1:0] bit functionality when the WGM4[3:0] bits are set to the fast PWM mode.
| COM4A[1]/COM4B[1] | COM4A[0]/COM4B[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC4A/OC4B disconnected. |
| 0 | 1 | WGM4[3:0] = 14 or 15: Toggle OC4A on Compare Match, OC4B disconnected (normal port operation). For all other WGM settings, normal port operation, OC4A/OC4B disconnected. |
| 1 | 0 | Clear OC4A/OC4B on Compare Match, set OC4A/OC4B at BOTTOM (non-inverting mode) |
| 1 | 1 | Set OC4A/OC4B on Compare Match, clear OC4A/OC4B at BOTTOM (inverting mode) |
- A special case occurs when OCR4A/OCR4B equals TOP and COM4A[1]/COM4B[1] is set. In this case, the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details.
The table below shows the COM4x[1:0] bit functionality when the WGM4[3:0] bits are set to the phase correct or the phase and frequency correct, PWM mode.
| COM4A[1]/COM4B[1] | COM4A[0]/COM4B[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC4A/OC4B disconnected. |
| 0 | 1 | WGM4[3:0] = 9 or 11: Toggle OC4A on Compare Match, OC4B disconnected (normal port operation). For all other WGM4 settings, normal port operation, OC4A/OC4B disconnected. |
| 1 | 0 | Clear OC4A/OC4B on Compare Match when up-counting. Set OC4A/OC4B on Compare Match when down-counting. |
| 1 | 1 | Set OC4A/OC4B on Compare Match when up-counting. Clear OC4A/OC4B on Compare Match when down-counting. |
- A special case occurs when OCR4A/OCR4B equals TOP and COM4A[1]/COM4B[1] is set. Refer to Phase Correct PWM Mode for details.
Bits 1:0 – WGM4[1:0] Waveform Generation Mode
Combined with the WGM4[3:2] bits found in the TCCR4B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are; Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See Modes of Operation).
|
Mode |
WGM4[3] |
WGM4[2] (CTC1)(1) |
WGM4[1] (PWM1[1])(1) |
WGM4[0] (PWM1[0])(1) |
Timer/Counter Mode of Operation |
TOP |
Update of OCR4x at |
TOV1 Flag Set on |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | Normal | 0xFFFF | Immediate | MAX |
| 1 | 0 | 0 | 0 | 1 | PWM, Phase Correct, 8-bit | 0x00FF | TOP | BOTTOM |
| 2 | 0 | 0 | 1 | 0 | PWM, Phase Correct, 9-bit | 0x01FF | TOP | BOTTOM |
| 3 | 0 | 0 | 1 | 1 | PWM, Phase Correct, 10-bit | 0x03FF | TOP | BOTTOM |
| 4 | 0 | 1 | 0 | 0 | CTC | OCR4A | Immediate | MAX |
| 5 | 0 | 1 | 0 | 1 | Fast PWM, 8-bit | 0x00FF | BOTTOM | TOP |
| 6 | 0 | 1 | 1 | 0 | Fast PWM, 9-bit | 0x01FF | BOTTOM | TOP |
| 7 | 0 | 1 | 1 | 1 | Fast PWM, 10-bit | 0x03FF | BOTTOM | TOP |
| 8 | 1 | 0 | 0 | 0 | PWM, Phase and Frequency Correct | ICR4 | BOTTOM | BOTTOM |
| 9 | 1 | 0 | 0 | 1 | PWM, Phase and Frequency Correct | OCR4A | BOTTOM | BOTTOM |
| 10 | 1 | 0 | 1 | 0 | PWM, Phase Correct | ICR4 | TOP | BOTTOM |
| 11 | 1 | 0 | 1 | 1 | PWM, Phase Correct | OCR4A | TOP | BOTTOM |
| 12 | 1 | 1 | 0 | 0 | CTC | ICR4 | Immediate | MAX |
| 13 | 1 | 1 | 0 | 1 | Reserved | - | - | - |
| 14 | 1 | 1 | 1 | 0 | Fast PWM | ICR4 | BOTTOM | TOP |
| 15 | 1 | 1 | 1 | 1 | Fast PWM | OCR4A | BOTTOM | TOP |
- The CTC1 and PWM1[1:0] bit definition names are obsolete. Use the WGM4[2:0] definitions. However, the functionality and location of these bits are compatible with previous versions of the timer.