19.11.8 TC3 Control Register A
| Name: | TCCR3A |
| Offset: | 0x90 |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| COM3A[1:0] | COM3B[1:0] | WGM3[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | |||
Bits 4:5, 6:7 – COM3 Compare Output Mode for Channel
The COM3A[1:0] and COM3B[1:0] control the Output Compare pins (OC3A and OC3B respectively) behavior. If one or both of the COM3A[1:0] bits are written to one, the OC3A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM3B[1:0] bit are written to one, the OC3B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC3A or OC3B pin must be set in order to enable the output driver.
When the OC3A or OC3B is connected to the pin, the function of the COM3n[1:0] bits is dependent on the WGM3[3:0] bits setting. The table below shows the COM3n[1:0] bit functionality when the WGM3[3:0] bits are set to a Normal or a CTC mode (non-PWM).
For OC3B or OC4B when not using the Output Compare Modulator, PORTD2 must also be set in order to enable the output.
| COM3A[1]/COM3B[1] | COM3A[0]/COM3B[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC3A/OC3B disconnected. |
| 0 | 1 | Toggle OC3A/OC3B on Compare Match. |
| 1 | 0 | Clear OC3A/OC3B on Compare Match (Set output to low level). |
| 1 | 1 | Set OC3A/OC3B on Compare Match (Set output to high level). |
The table below shows the COM1x[1:0] bit functionality when the WGM3[3:0] bits are set to the fast PWM mode.
| COM3A[1]/COM3B[1] | COM3A0/COM3B[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC3A/OC3B disconnected. |
| 0 | 1 | WGM3[3:0] = 14 or 15: Toggle OC3A on Compare Match, OC3B disconnected (normal port operation). For all other WGM3 settings, normal port operation, OC3A/OC3B disconnected. |
| 1 | 0 | Clear OC3A/OC3B on Compare Match, set OC3A/OC3B at BOTTOM (non-inverting mode) |
| 1 | 1 | Set OC3A/OC3B on Compare Match, clear OC3A/OC3B at BOTTOM (inverting mode) |
- A special case occurs when OCR3A/OCR3B equals TOP and COM3A[1]/COM3B[1] is set. In this case, the compare match is ignored but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details.
The table below shows the COM3x[1:0] bit functionality when the WGM3[3:0] bits are set to the phase correct or the phase and frequency correct, PWM mode.
| COM3A[1]/COM3B[1] | COM3A[0]/COM3B[0] | Description |
|---|---|---|
| 0 | 0 | Normal port operation, OC3A/OC3B disconnected. |
| 0 | 1 | WGM3[3:0] = 9 or 11: Toggle OC3A on Compare Match, OC3B disconnected (normal port operation). For all other WGM3 settings, normal port operation, OC3A/OC3B disconnected. |
| 1 | 0 | Clear OC3A/OC3B on Compare Match when up-counting. Set OC3A/OC3B on Compare Match when down-counting. |
| 1 | 1 | Set OC3A/OC3B on Compare Match when up-counting. Clear OC3A/OC3B on Compare Match when down-counting. |
- A special case occurs when OCR3A/OCR3B equals TOP and COM3A[1]/COM3B[1] is set. Refer to Phase Correct PWM Mode for details.
Bits 1:0 – WGM3[1:0] Waveform Generation Mode
Combined with the WGM3[3:2] bits found in the TCCR3B Register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See Modes of Operation).
|
Mode |
WGM3[3] |
WGM3[2] (CTC1)(1) |
WGM3[1] (PWM1[1])(1) |
WGM3[0] (PWM1[0])(1) |
Timer/Counter Mode of Operation |
TOP |
Update of OCR1x at |
TOV1 Flag Set on |
|---|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | Normal | 0xFFFF | Immediate | MAX |
| 1 | 0 | 0 | 0 | 1 | PWM, Phase Correct, 8-bit | 0x00FF | TOP | BOTTOM |
| 2 | 0 | 0 | 1 | 0 | PWM, Phase Correct, 9-bit | 0x01FF | TOP | BOTTOM |
| 3 | 0 | 0 | 1 | 1 | PWM, Phase Correct, 10-bit | 0x03FF | TOP | BOTTOM |
| 4 | 0 | 1 | 0 | 0 | CTC | OCR3A | Immediate | MAX |
| 5 | 0 | 1 | 0 | 1 | Fast PWM, 8-bit | 0x00FF | BOTTOM | TOP |
| 6 | 0 | 1 | 1 | 0 | Fast PWM, 9-bit | 0x01FF | BOTTOM | TOP |
| 7 | 0 | 1 | 1 | 1 | Fast PWM, 10-bit | 0x03FF | BOTTOM | TOP |
| 8 | 1 | 0 | 0 | 0 | PWM, Phase and Frequency Correct | ICR1 | BOTTOM | BOTTOM |
| 9 | 1 | 0 | 0 | 1 | PWM, Phase and Frequency Correct | OCR3A | BOTTOM | BOTTOM |
| 10 | 1 | 0 | 1 | 0 | PWM, Phase Correct | ICR3 | TOP | BOTTOM |
| 11 | 1 | 0 | 1 | 1 | PWM, Phase Correct | OCR3A | TOP | BOTTOM |
| 12 | 1 | 1 | 0 | 0 | CTC | ICR3 | Immediate | MAX |
| 13 | 1 | 1 | 0 | 1 | Reserved | - | - | - |
| 14 | 1 | 1 | 1 | 0 | Fast PWM | ICR3 | BOTTOM | TOP |
| 15 | 1 | 1 | 1 | 1 | Fast PWM | OCR3A | BOTTOM | TOP |
- The CTC1 and PWM1[1:0] bit definition names are obsolete. Use the WGM3[2:0] definitions. However, the functionality and location of these bits are compatible with previous versions of the timer.