19.11.2 TC1 Control Register B

Name: TCCR1B
Offset: 0x81
Reset: 0x00
Property: -

Bit 76543210 
 ICNC1ICES1 WGM1[3]WGM1[2]CS1[2:0] 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 7 – ICNC1 Input Capture Noise Canceler

Writing this bit to '1' activates the input capture noise canceler. When the noise canceler is activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four successive equal valued samples of the ICP1 pin for changing its output. The input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled.

Bit 6 – ICES1 Input Capture Edge Select

This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture event. When the ICES1 bit is written to zero, a falling (negative) edge is used as a trigger, and when the ICES1 bit is written to '1', a rising (positive) edge will trigger the capture.

When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1) and this can be used to cause an input capture interrupt, if this interrupt is enabled.

When the ICR1 is used as TOP value (see description of the WGM1[3:0] bits located in the TCCR1A and the TCCR1B register), the ICP1 is disconnected and consequently, the input capture function is disabled.

Bits 3, 4 – WGM1 Waveform Generation Mode

Refer to TCCR1A.

Bits 2:0 – CS1[2:0] Clock Select 1

The three clock select bits select the clock source to be used by the Timer/Counter. Refer to Figure 19-9 and Figure 19-10.

Table 19-7. Clock Select Bit Description
CS1[2]CS1[1]CS1[0]Description
000No clock source (Timer/Counter stopped).
001clkI/O/1 (No prescaling)
010clkI/O/8 (From prescaler)
011clkI/O/64 (From prescaler)
100clkI/O/256 (From prescaler)
101clkI/O/1024 (From prescaler)
110External clock source on T1 pin. Clock on falling edge.
111External clock source on T1 pin. Clock on rising edge.