19.11.1 TC1 Control Register A

Name: TCCR1A
Offset: 0x80
Reset: 0x00
Property: -

Bit 76543210 
 COM1A[1:0]COM1B[1:0]  WGM1[1:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 4:5, 6:7 – COM1 Compare Output Mode for Channel

The COM1A[1:0] and COM1B[1:0] control the output compare pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A[1:0] bits are written to one, the OC1A output overrides the normal port functionality of the I/O pin it is connected to. If one or both of the COM1B[1:0] bit are written to one, the OC1B output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver.

When the OC1A or OC1B is connected to the pin, the function of the COM1x[1:0] bits is dependent on the WGM1[3:0] bits setting. The table below shows the COM1x[1:0] bit functionality when the WGM1[3:0] bits are set to a Normal or a CTC mode (non-PWM).

Table 19-4. Compare Output Mode, Non-PWM
COM1A[1]/COM1B[1]COM1A[0]/COM1B[0]Description
00Normal port operation, OC1A/OC1B disconnected.
01Toggle OC1A/OC1B on compare match.
10Clear OC1A/OC1B on compare match (Set output to low level).
11Set OC1A/OC1B on compare match (Set output to high level).

The table below shows the COM1x[1:0] bit functionality when the WGM1[3:0] bits are set to the fast PWM mode.

Table 19-5. Compare Output Mode, Fast PWM
COM1A[1]/COM1B[1]COM1A[0]/COM1B[0]Description
00Normal port operation, OC1A/OC1B disconnected.
01WGM1[3:0] = 14 or 15: Toggle OC1A on compare match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
10Clear OC1A/OC1B on compare match, set OC1A/OC1B at BOTTOM (Non-inverting mode)
11Set OC1A/OC1B on compare match, clear OC1A/OC1B at BOTTOM (Inverting mode)
Note:
  1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A[1]/COM1B[1] is set. In this case the compare match is ignored, but the set or clear is done at BOTTOM. Refer to Fast PWM Mode for details.

The table below shows the COM1x[1:0] bit functionality when the WGM1[3:0] bits are set to the phase correct or the phase and frequency correct, PWM mode.

Table 19-6. Compare Output Mode, Phase Correct, and Phase and Frequency Correct PWM
COM1A[1]/COM1B[1]COM1A[0]/COM1B[0]Description
00Normal port operation, OC1A/OC1B disconnected.
01WGM1[3:0] = 9 or 11: Toggle OC1A on compare match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected.
10Clear OC1A/OC1B on compare match when up-counting. Set OC1A/OC1B on compare match when down-counting.
11Set OC1A/OC1B on compare match when up-counting. Clear OC1A/OC1B on compare match when down-counting.
Note:
  1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A[1]/COM1B[1] is set. Refer to Phase Correct PWM Mode for details.

Bits 1:0 – WGM1[1:0] Waveform Generation Mode

Combined with the WGM1[3:2] bits found in the TCCR1B register, these bits control the counting sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used. Modes of operation supported by the Timer/Counter unit are; Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. (See Modes of Operation).

Table 19-3. Waveform Generation Mode Bit Description

Mode

WGM1[3]

WGM1[2]

(CTC1)(1)

WGM1[1]

(PWM1[1])(1)

WGM1[0]

(PWM1[0])(1)

Timer/Counter

Mode of Operation

TOP

Update of

OCR1x at

TOV1 Flag

Set on

00000Normal0xFFFFImmediateMAX
10001PWM, Phase Correct, 8-bit0x00FFTOPBOTTOM
20010PWM, Phase Correct, 9-bit0x01FFTOPBOTTOM
30011PWM, Phase Correct, 10-bit0x03FFTOPBOTTOM
40100CTCOCR1AImmediateMAX
50101Fast PWM, 8-bit0x00FFBOTTOMTOP
60110Fast PWM, 9-bit0x01FFBOTTOMTOP
70111Fast PWM, 10-bit0x03FFBOTTOMTOP
81000PWM, Phase and Frequency CorrectICR1BOTTOMBOTTOM
91001PWM, Phase and Frequency CorrectOCR1ABOTTOMBOTTOM
101010PWM, Phase CorrectICR1TOPBOTTOM
111011PWM, Phase CorrectOCR1ATOPBOTTOM
121100CTCICR1ImmediateMAX
131101Reserved---
141110Fast PWMICR1BOTTOMTOP
151111Fast PWMOCR1ABOTTOMTOP
Note:
  1. The CTC1 and PWM1[1:0] bit definition names are obsolete. Use the WGM1[3:0] definitions. However, the functionality and location of these bits are compatible with previous versions of the timer.