19.11.22 Timer/Counter 1 Interrupt Mask
Register
| Name: | TIMSK1 |
| Offset: | 0x6F |
| Reset: | 0x00 |
| Property: | - |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | ICIE1 | | | OCIE1B | OCIE1A | TOIE1 | |
| Access | | | R/W | | | R/W | R/W | R/W | |
| Reset | | | 0 | | | 0 | 0 | 0 | |
Bit 5 – ICIE1 Timer/Counter 1,
Input Capture Interrupt Enable
When this bit is
written to '1', and the I-flag in the Status register is set (interrupts globally
enabled), the Timer/Counter 1 Input Capture interrupt is enabled. The corresponding
Interrupt Vector is executed when the ICF1 flag, located in TIFR1, is
set.
Bit 2 – OCIE1B Timer/Counter 1,
Output Compare B Match Interrupt Enable
When this bit is
written to '1', and the I-flag in the Status register is set (interrupts globally
enabled), the Timer/Counter 1 Output Compare B Match interrupt is enabled. The
corresponding interrupt vector is executed when the OCF1B flag, located in TIFR1, is
set.
Bit 1 – OCIE1A Timer/Counter 1,
Output Compare A Match Interrupt Enable
When this bit is
written to '1', and the I-flag in the Status register is set (interrupts globally
enabled), the Timer/Counter 1 Output Compare A Match interrupt is enabled. The
corresponding Interrupt Vector is executed when the OCF1A Flag, located in TIFR1, is
set.
Bit 0 – TOIE1 Timer/Counter 1,
Overflow Interrupt Enable
When this bit is
written to '1', and the I-flag in the Status register is set (interrupts globally
enabled), the Timer/Counter 1 Overflow interrupt is enabled. The corresponding
interrupt vector is executed when the TOV flag, located in TIFR1, is
set.
