45.7.10 USART Interrupt Disable Register (SPI_MODE)

This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.

The following configuration values are valid for all listed bit names of this register:

0: No effect

1: Disables the corresponding interrupt.

Name: US_IDR (SPI_MODE)
Offset: 0x000C
Property: Write-only

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
     NSSE    
Access W 
Reset  
Bit 15141312111098 
      UNRETXEMPTY  
Access WW 
Reset  
Bit 76543210 
   OVRE   TXRDYRXRDY 
Access WWW 
Reset  

Bit 19 – NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Disable

Bit 10 – UNRE SPI Underrun Error Interrupt Disable

Bit 9 – TXEMPTY TXEMPTY Interrupt Disable

Bit 5 – OVRE Overrun Error Interrupt Disable

Bit 1 – TXRDY TXRDY Interrupt Disable

Bit 0 – RXRDY RXRDY Interrupt Disable