This register is relevant only if USART_MODE = 0x9 in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: No effect
1: Enables the corresponding interrupt.
Name:
US_IER (LON_MODE)
Offset:
0x0008
Property:
Write-only
Bit
31
30
29
28
27
26
25
24
LBLOVFE
LRXD
LFET
LCOL
LTXD
Access
W
W
W
W
W
Reset
Bit
23
22
21
20
19
18
17
16
Access
Reset
Bit
15
14
13
12
11
10
9
8
UNRE
TXEMPTY
Access
W
W
Reset
Bit
7
6
5
4
3
2
1
0
LCRCE
LSFE
OVRE
TXRDY
RXRDY
Access
W
W
W
W
W
Reset
Bit 28 – LBLOVFE LON Backlog Overflow Error Interrupt Enable
Bit 27 – LRXD LON Reception Done Interrupt Enable
Bit 26 – LFET LON Frame Early Termination Interrupt Enable
Bit 25 – LCOL LON Collision Interrupt Enable
Bit 24 – LTXD LON Transmission Done Interrupt Enable
Bit 10 – UNRE Underrun Error Interrupt Enable
Bit 9 – TXEMPTY TXEMPTY Interrupt Enable
Bit 7 – LCRCE LON CRC Error Interrupt Enable
Bit 6 – LSFE LON Short Frame Error Interrupt Enable
Bit 5 – OVRE Overrun Error Interrupt Enable
Bit 1 – TXRDY TXRDY Interrupt Enable
Bit 0 – RXRDY RXRDY Interrupt Enable
The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.