45.7.25 USART Transmitter Timeguard Register
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
For LON specific configuration, see “USART Transmitter Timeguard Register (LON_MODE)”.
| Name: | US_TTGR |
| Offset: | 0x0028 |
| Reset: | 0x0 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| TG[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
Bits 7:0 – TG[7:0] Timeguard Value
| Value | Description |
|---|---|
| 0 | The transmitter timeguard is disabled. |
| 1–255 | The transmitter timeguard is enabled and TG is Timeguard Delay / Bit Period. |