45.7.24 USART Receiver Timeout Register

This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.

Name: US_RTOR
Offset: 0x0024
Reset: 0x0
Property: Read/Write

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
        TO[16] 
Access R/W 
Reset 0 
Bit 15141312111098 
 TO[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 TO[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bits 16:0 – TO[16:0] Timeout Value

ValueDescription
0

The receiver timeout is disabled.

1–65535

The receiver timeout is enabled and TO is Timeout Delay / Bit Period.

1–131071

The receiver timeout is enabled and TO is Timeout Delay / Bit Period.