45.7.31 USART Manchester Configuration Register
This register can only be written if the WPEN bit is cleared in the USART Write Protection Mode Register.
Name: | US_MAN |
Offset: | 0x0050 |
Reset: | 0xB30011004 |
Property: | Read/Write |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
RXIDLEV | DRIFT | ONE | RX_MPOL | RX_PP[1:0] | |||||
Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
Reset | 0 | 0 | 1 | 1 | 0 | 0 |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
RX_PL[3:0] | |||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 0 | 0 | 1 |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
TX_MPOL | TX_PP[1:0] | ||||||||
Access | R/W | R/W | R/W | ||||||
Reset | 1 | 0 | 0 |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
TX_PL[3:0] | |||||||||
Access | R/W | R/W | R/W | R/W | |||||
Reset | 0 | 1 | 0 | 0 |
Bit 31 – RXIDLEV Receiver Idle Value
Value | Description |
---|---|
0 | Receiver line idle value is 0. |
1 | Receiver line idle value is 1. |
Bit 30 – DRIFT Drift Compensation
Value | Description |
---|---|
0 | The USART cannot recover from an important clock drift |
1 | The USART can recover from clock drift. The 16X clock mode must be enabled. |
Bit 29 – ONE Must Be Set to 1
Bit 29 must always be set to 1 when programming the US_MAN register.
Bit 28 – RX_MPOL Receiver Manchester Polarity
Value | Description |
---|---|
0 | Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition. |
1 | Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero-to-one transition. |
Bits 25:24 – RX_PP[1:0] Receiver Preamble Pattern detected
The following values assume that RX_MPOL field is not set:
Value | Name | Description |
---|---|---|
00 | ALL_ONE | The preamble is composed of ‘1’s |
01 | ALL_ZERO | The preamble is composed of ‘0’s |
10 | ZERO_ONE | The preamble is composed of ‘01’s |
11 | ONE_ZERO | The preamble is composed of ‘10’s |
Bits 19:16 – RX_PL[3:0] Receiver Preamble Length
Value | Description |
---|---|
0 | The receiver preamble pattern detection is disabled |
1–15 | The detected preamble length is RX_PL × Bit Period |
Bit 12 – TX_MPOL Transmitter Manchester Polarity
Value | Description |
---|---|
0 | Logic zero is coded as a zero-to-one transition, Logic one is coded as a one-to-zero transition. |
1 | Logic zero is coded as a one-to-zero transition, Logic one is coded as a zero-to-one transition. |
Bits 9:8 – TX_PP[1:0] Transmitter Preamble Pattern
The following values assume that TX_MPOL field is not set:
Value | Name | Description |
---|---|---|
0 | ALL_ONE | The preamble is composed of ‘1’s |
1 | ALL_ZERO | The preamble is composed of ‘0’s |
2 | ZERO_ONE | The preamble is composed of ‘01’s |
3 | ONE_ZERO | The preamble is composed of ‘10’s |
Bits 3:0 – TX_PL[3:0] Transmitter Preamble Length
Value | Description |
---|---|
0 | The transmitter preamble pattern generation is disabled |
1–15 | The preamble length is TX_PL × Bit Period |