45.7.16 USART Interrupt Mask Register (LON_MODE)
This configuration is relevant only if USART_MODE = 0x9 in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
Name: | US_IMR (LON_MODE) |
Offset: | 0x0010 |
Reset: | 0x0 |
Property: | Read-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | LBLOVFE | LRXD | LFET | LCOL | LTXD | |
Access | | | | R | R | R | R | R | |
Reset | | | | 0 | 0 | 0 | 0 | 0 | |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | |
Access | | | | | | | | | |
Reset | | | | | | | | | |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | UNRE | TXEMPTY | | |
Access | | | | | | R | R | | |
Reset | | | | | | 0 | 0 | | |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| LCRCE | LSFE | OVRE | | | | TXRDY | RXRDY | |
Access | R | R | R | | | | R | R | |
Reset | 0 | 0 | 0 | | | | 0 | 0 | |
Bit 28 – LBLOVFE LON Backlog Overflow Error Interrupt Mask
Bit 27 – LRXD LON Reception Done Interrupt Mask
Bit 26 – LFET LON Frame Early Termination Interrupt Mask
Bit 25 – LCOL LON Collision Interrupt Mask
Bit 24 – LTXD LON Transmission Done Interrupt Mask
Bit 10 – UNRE Underrun Error Interrupt Mask
Bit 9 – TXEMPTY TXEMPTY Interrupt Mask
Bit 7 – LCRCE LON CRC Error Interrupt Mask
Bit 6 – LSFE LON Short Frame Error Interrupt Mask
Bit 5 – OVRE Overrun Error Interrupt Mask
Bit 1 – TXRDY TXRDY Interrupt Mask
Bit 0 – RXRDY RXRDY Interrupt Mask