45.7.17 USART Channel Status Register
For SPI specific configuration, see “USART Channel Status Register (SPI_MODE)”.
For LIN specific configuration, see “USART Channel Status Register (LIN_MODE)”.
For LON specific configuration, see “USART Channel Status Register (LON_MODE)”.
| Name: | US_CSR |
| Offset: | 0x0014 |
| Reset: | 0x0 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| MANERR | |||||||||
| Access | R | ||||||||
| Reset | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| CTS | DCD | DSR | RI | CTSIC | DCDIC | DSRIC | RIIC | ||
| Access | R | R | R | R | R | R | R | R | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| NACK | ITER | TXEMPTY | TIMEOUT | ||||||
| Access | R | R | R | R | |||||
| Reset | 0 | 0 | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PARE | FRAME | OVRE | RXBRK | TXRDY | RXRDY | ||||
| Access | R | R | R | R | R | R | |||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 24 – MANERR Manchester Error (cleared by writing a one to the bit US_CR.RSTSTA)
| Value | Description |
|---|---|
| 0 | No Manchester error has been detected since the last RSTSTA. |
| 1 | At least one Manchester error has been detected since the last RSTSTA. |
Bit 23 – CTS Image of CTS Input
| Value | Description |
|---|---|
| 0 | CTS input is driven low. |
| 1 | CTS input is driven high. |
Bit 22 – DCD Image of DCD Input
| Value | Description |
|---|---|
| 0 | DCD input is driven low. |
| 1 | DCD input is driven high. |
Bit 21 – DSR Image of DSR Input
| Value | Description |
|---|---|
| 0 | DSR input is driven low. |
| 1 | DSR input is driven high. |
Bit 20 – RI Image of RI Input
| Value | Description |
|---|---|
| 0 | RI input is driven low. |
| 1 | RI input is driven high. |
Bit 19 – CTSIC Clear to Send Input Change Flag (cleared on read)
| Value | Description |
|---|---|
| 0 | No input change has been detected on the CTS pin since the last read of US_CSR. |
| 1 | At least one input change has been detected on the CTS pin since the last read of US_CSR. |
Bit 18 – DCDIC Data Carrier Detect Input Change Flag (cleared on read)
| Value | Description |
|---|---|
| 0 | No input change has been detected on the DCD pin since the last read of US_CSR. |
| 1 | At least one input change has been detected on the DCD pin since the last read of US_CSR. |
Bit 17 – DSRIC Data Set Ready Input Change Flag (cleared on read)
| Value | Description |
|---|---|
| 0 | No input change has been detected on the DSR pin since the last read of US_CSR. |
| 1 | At least one input change has been detected on the DSR pin since the last read of US_CSR. |
Bit 16 – RIIC Ring Indicator Input Change Flag (cleared on read)
| Value | Description |
|---|---|
| 0 | No input change has been detected on the RI pin since the last read of US_CSR. |
| 1 | At least one input change has been detected on the RI pin since the last read of US_CSR. |
Bit 13 – NACK Non Acknowledge Interrupt (cleared by writing a one to bit US_CR.RSTNACK)
| Value | Description |
|---|---|
| 0 | Non acknowledge has not been detected since the last RSTNACK. |
| 1 | At least one non acknowledge has been detected since the last RSTNACK. |
Bit 10 – ITER Max Number of Repetitions Reached (cleared by writing a one to bit US_CR.RSTIT)
| Value | Description |
|---|---|
| 0 | Maximum number of repetitions has not been reached since the last RSTIT. |
| 1 | Maximum number of repetitions has been reached since the last RSTIT. |
Bit 9 – TXEMPTY Transmitter Empty (cleared by writing US_THR)
| Value | Description |
|---|---|
| 0 | There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. |
| 1 | There are no characters in US_THR, nor in the Transmit Shift Register. |
Bit 8 – TIMEOUT Receiver Timeout (cleared by writing a one to bit US_CR.STTTO)
| Value | Description |
|---|---|
| 0 | There has not been a timeout since the last Start Timeout command (STTTO in US_CR) or the Timeout Register is 0. |
| 1 | There has been a timeout since the last Start Timeout command (STTTO in US_CR). |
Bit 7 – PARE Parity Error (cleared by writing a one to bit US_CR.RSTSTA)
| Value | Description |
|---|---|
| 0 | No parity error has been detected since the last RSTSTA. |
| 1 | At least one parity error has been detected since the last RSTSTA. |
Bit 6 – FRAME Framing Error (cleared by writing a one to bit US_CR.RSTSTA)
| Value | Description |
|---|---|
| 0 | No stop bit has been detected low since the last RSTSTA. |
| 1 | At least one stop bit has been detected low since the last RSTSTA. |
Bit 5 – OVRE Overrun Error (cleared by writing a one to bit US_CR.RSTSTA)
| Value | Description |
|---|---|
| 0 | No overrun error has occurred since the last RSTSTA. |
| 1 | At least one overrun error has occurred since the last RSTSTA. |
Bit 2 – RXBRK Break Received/End of Break (cleared by writing a one to bit US_CR.RSTSTA)
| Value | Description |
|---|---|
| 0 | No break received or end of break detected since the last RSTSTA. |
| 1 | Break received or end of break detected since the last RSTSTA. |
Bit 1 – TXRDY Transmitter Ready (cleared by writing US_THR)
| Value | Description |
|---|---|
| 0 | A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. |
| 1 | There is no character in the US_THR. |
Bit 0 – RXRDY Receiver Ready (cleared by reading US_RHR)
| Value | Description |
|---|---|
| 0 | No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. |
| 1 | At least one complete character has been received and US_RHR has not yet been read. |