45.7.14 USART Interrupt Mask Register (SPI_MODE)
This configuration is relevant only if USART_MODE = 0xE or 0xF in the USART Mode Register.
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
| Name: | US_IMR (SPI_MODE) |
| Offset: | 0x0010 |
| Reset: | 0x0 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | NSSE | | | | |
| Access | | | | | R | | | | |
| Reset | | | | | 0 | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | UNRE | TXEMPTY | | |
| Access | | | | | | R | R | | |
| Reset | | | | | | 0 | 0 | | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | OVRE | | | | TXRDY | RXRDY | |
| Access | | | R | | | | R | R | |
| Reset | | | 0 | | | | 0 | 0 | |
Bit 19 – NSSE NSS Line (Driving CTS Pin) Rising or Falling Edge Event Interrupt Mask
Bit 10 – UNRE SPI Underrun Error Interrupt Mask
Bit 9 – TXEMPTY TXEMPTY Interrupt Mask
Bit 5 – OVRE Overrun Error Interrupt Mask
Bit 1 – TXRDY TXRDY Interrupt Mask
Bit 0 – RXRDY RXRDY Interrupt Mask
