21.2 Register Types
The following table lists the several register types in the SYSREG block.
| Type | Function |
|---|---|
| RW-P | Supports read and write accesses via AHB bus matrix. See Figure 21-5. Register contents are initialized from Flash configuration bits at power-up and the assertion of SYS_RESET_N. Typically used for MSS Control Registers. |
| RW | Supports read and write accesses via AHB bus
matrix. See Figure 21-5. Register contents are not initialized from Flash configuration bits at power-up. The reset state is determined by the user HW design following assertion of SYS_RESET_N. Typically used for MSS Control Registers. |
| RO | Supports read-only accesses via AHB bus matrix. See Figure 21-6. Register contents are not initialized from Flash configuration bits at power-up or the assertion of SYS_RESET_N. Typically used for MSS Control Registers. |
| RO-U | Does not support read or write access via AHB
bus matrix. See Figure 21-8. Register contents are initialized from Flash configuration bits at power-up and the assertion of SYS_RESET_N. Typically used for MSS Control Registers. |
| RO-P | Supports read-only accesses via AHB bus
matrix. See Figure 21-7. Register contents are initialized from Flash configuration bits at power-up and the assertion of SYS_RESET_N. Typically used to return MSS status information. |
| W1P | Write '1' to clear the register. This register is Write-Only. |
| SW1C | Individual register bits are set ('1') when related input is asserted. Bits are individually cleared when corresponding register bit is written high. |
The following figures show schematically a few of the register types of the SYSREG registers.