21.4 Register Map

The following table lists all the registers in the SYSREG block. The SYSREG block is located at address 0x40038000 in Cortex-M3 processor address space.

Table 21-2. SYSREG
Register NameAddr.

Offset

Register TypeFlash Write ProtectReset SourceDescription
Table 21-40x0RW-PRegisterSYSRESET_NControls address mapping of the eSRAMs
Table 21-50x4RW-PRegisterSYSRESET_NeSRAM0 and eSRAM1 maximum latency
Table 21-70x8RW-PRegisterSYSRESET_NDDR Configuration Register
Table 21-80XCRW-PRegisterSYSRESET_NeNVM Configuration Register
Table 21-100x10RW-PRegisterSYSRESET_NeNVM Remap Base Address Control Register
Table 21-110x14RW-PRegisterSYSRESET_NeNVM Remap Base Address Control Register
Table 21-120x18RW-PRegisterSYSRESET_NUsed to configure cache
Table 21-130x1CRW-PRegisterSYSRESET_NCache Region Control Register
Table 21-140x24RW-PRegisterSYSRESET_NCache Flush Index Control Register
Table 21-150x28RW-PRegisterSYSRESET_NDDR write buffer timeout
Table 21-160x2CRW-PRegisterSYSRESET_NDDR non-bufferable address region base address
Table 21-170x30RW-PRegisterSYSRESET_NSize of non- bufferable address region
Table 21-190x34RW-PRegisterSYSRESET_NMSS DDR bridge Configuration Register
Table 21-200x38RW-PRegisterSYSRESET_NEDAC Configuration Register for eSRAM0, eSRAM1, USB, MAC, and CAN
Table 21-210x3CRW-PRegisterSYSRESET_NMaster Weight Configuration Register 0
Table 21-220x40RW-PRegisterSYSRESET_NMaster Weight Configuration Register 1
Table 21-240x44RW-PRegisterSYSRESET_NEnables software interrupt
Table 21-250x48RW-PBitSYSRESET_NSoftware Reset Control Register
Table 21-260x4CRW-PRegisterSYSRESET_NCortex M3 Configuration Register
Table 21-270x50RW-PRegisterSYSRESET_NControls fabric interface
Table 21-280x54RW-PRegisterSYSRESET_NControls MSS peripherals
Table 21-290x58RW-PRegisterPORESET_NConfigures GPIO system reset
Table 21-300x5CRW-PRegisterPORESET_NGPIO Input Source Select Control Register
Table 21-310x60RW-PRegisterPORESET_NMDDR Configuration Register
Table 21-320x64RW-PRegisterPORESET_NConfigures USB data interfaces from IOMUXCELLs and I/O pads
Table 21-330x68RW-PRegisterPORESET_NPeripheral Clock MUX Select Control Register
Table 21-340x6CRW-PRegisterPORESET_NConfigures Watchdog timer
Table 21-350x70RW-PRegisterPORESET_NMDDR I/O Calibration Control Register
Reserved0x74
Table 21-360x78RW-PRegisterSYSRESET_NEnables/disables 1-bit error, 2-bit error status for eSRAM0, eSRAM1, USB, CAN, and MAC
Table 21-370x7CRW-PRegisterSYSRESET_NConfigures USB interface
Table 21-380x80RW-PRegisterSYSRESET_NControls the pipeline present in the memory read path of eSRAM memory
Table 21-390x84RW-PRegisterSYSRESET_NMSS Interrupt Enable Control Register
Table 21-400x88RW-PRegisterSYSRESET_NConfigures RTC timer WAKEUP signal
Table 21-410x8CRW-PRegisterSYSRESET_NMAC Configuration Register
Table 21-420x90RW-PRegisterCC_RESET_NControls the configuration input of MPLL register
Table 21-440x94RW-PRegisterCC_RESET_NControls the configuration input of MPLL register
Table 21-450x98RW-PFieldCC_RESET_NMSS DDR bridge FACC1 Configuration Register
Table 21-470x9CRW-PFieldCC_RESET_NMSS DDR bridge FACC2 Configuration Register
Table 21-480xA0RW-PRegisterCC_RESET_NPPL Lock Enable Control Register
Table 21-490xA4RW-PRegisterSYSRESET_NStarts FPGA fabric calibration test circuit
Table 21-500xA8RW-PRegisterSYSRESET_NPLL Delay Line Select Control Register
Table 21-510xACRW-PRegisterSYSRESET_NMAC status clear on read
Table 21-520xB0RWReset Source Control Register
Table 21-530xB4ROSYSRESET_NDcode Bus Error Address Status Register
Table 21-540xB8ROSYSRESET_NIcode Bus Error Address Status Register
Table 21-550xBCROSYSRESET_NSystem Bus Error Address Status Register
Reserved0xC0SYSRESET_N
Table 21-560xC4ROSYSRESET_NICode Miss Control Status Register
Table 21-570xC8ROSYSRESET_NICode Hit Control Status Register
Table 21-580xCCROSYSRESET_NDCode Miss Control Status Register
Table 21-590xD0ROSYSRESET_NDCode Hit Control Status Register
Table 21-600xD4ROSYSRESET_NICode Transaction Count Control Status Register
Table 21-610xD8ROSYSRESET_NDCode Transaction count Control Status Register
Table 21-620xDCROSYSRESET_NMSS DDR Bridge DS Master Error Address Status Register
Table 21-630xE0ROSYSRESET_NMSS DDR Bridge High Performance DMA Master Error Address Status Register
Table 21-640xE4ROSYSRESET_NMSS DDR Bridge AHB Bus Error Address Status Register
Table 21-650xE8ROSYSRESET_NMSS DDR Bridge Buffer Empty Status Register
Table 21-660xECROSYSRESET_NMSS DDR Bridge Disable Buffer Status Register
Table 21-670xF0ROSYSRESET_N1-bit error and 2-bit error count of eSRAM0
Table 21-680xF4ROSYSRESET_N1-bit error and 2-bit error count of eSRAM1
Reserved0xF8SYSRESET_N
Table 21-690xFCROSYSRESET_N1-bit error and 2-bit error count of MAC transmitter
Table 21-700x100ROSYSRESET_N1-bit error and 2-bit error count of MAC receiver
Table 21-710x104ROSYSRESET_N1-bit error and 2-bit error count of USB
Table 21-720x108ROSYSRESET_N1-bit error and 2-bit error count of CAN
Table 21-730x10CROSYSRESET_NAddress from eSRAM0 on which 1-bit and 2-bit SECDED error has occurred
Table 21-740x110ROSYSRESET_NAddress from eSRAM1 on which 1-bit and 2-bit SECDED error has occurred
Table 21-750x114ROSYSRESET_NAddress from MAC receiver on which 1-bit and 2-bit SECDED error has occurred
Table 21-760x118ROSYSRESET_NAddress from MAC transmitter on which 1-bit and 2 bit SECDED error has occurred.
Table 21-770x11CROSYSRESET_NAddress from CAN on which 1-bit and 2-bit SECDED error has occurred
Table 21-780x120ROSYSRESET_NAddress from USB on which 1-bit and 2-bit SECDED error has occurred
Table 21-790x124RO-USYSRESET_NRead and write security for masters 0, 1, and 2 to eSRAM0, eSRAM1, eNVM1, eNVM0, and MSS DDR bridge
Table 21-800x128RO-USYSRESET_NRead and write security for masters 4, 5, and DDR_FIC to eSRAM0, eSRAM1, eNVM1, eNVM0, and MSS DDR bridge
Table 21-810x12CRO-USYSRESET_NRead and write security for masters 3, 6, 7, and 8 to eSRAM0, eSRAM1, eNVM1, eNVM0, and MSS DDR bridge
Table 21-820x130RO-USYSRESET_NRead and write security for master 9 to eSRAM0, eSRAM1, eNVM1, eNVM0, and MSS DDR bridge
Table 21-830x134ROSYSRESET_NCortex-M3 processor Status Register
Table 21-840x138ROSYSRESET_NETM count for lower bits [31:0]
Table 21-850x13CROSYSRESET_NETM count for higher bits [47:32]
Table 21-860x140ROSYSRESET_NDevice Status Register
Table 21-870x144RO-USYSRESET_NConfiguration for accessibility of protect regions of eNVM0 and eNVM1
Table 21-880x148RO-UPORESET_NCode shadow Status Register
Table 21-890x14CROConfigures device version
Table 21-900x150ROMSS DDR PLL Status Register
Table 21-910x154ROSYSRESET_NUSB Status Register
Table 21-920x158ROSYSRESET_NBusy status eNVM0 and eNVM1
Reserved0x15C
Table 21-930x160ROSYSRESET_NMSS DDR bridges status
Table 21-940x164ROPORESET_NDDR I/O Calibration Status Register
Table 21-950x168ROSYSRESET_NMSS DDR Clock Calibration Status Register
Table 21-960x16CRO-PPORESET_NConfigures Watchdog load value
Table 21-970x170RO-PPORESET_NConfigures Watchdog MVRP value
Table 21-980x174RO-PSYSRESET_NUser Configuration Register 0
Table 21-990x178RO-PSYSRESET_NUser Configuration Register 1
Table 21-1000x17CRO-PSYSRESET_NUser Configuration Register 2
Table 21-1010x180RO-PSYSRESET_NUser Configuration Register 3
Table 21-1020x184RO-PSYSRESET_NSize of memory protected from fabric master
Table 21-1040x188RO-PSYSRESET_NBase address which is protected from fabric master
Table 21-1050x18CRO-PSYSRESET_NMSS GPIO Definition Register
Table 21-1060x190SW1CSYSRESET_NStatus of 1-bit SECDED error detection and correction, 2-bit SECDED error detection for eSRAM0, eSRAM1, MAC, USB, and CAN
Table 21-1070x194SW1CSYSRESET_NMSS Internal Status Register
Table 21-1080x198SW1CSYSRESET_NMSS External Status Register
Table 21-1090x19CSW1CPORESET_NWatchdog Time out event register
Table 21-1100x1A0W1PSYSRESET_NClear MSS counters
Table 21-1110x1A4W1PSYSRESET_NClears 16-bit counter value in eSRAM0, eSRAM1, MAC, USB, and CAN corresponding to count value of EDAC 1-bit and 2-bit errors
Table 21-1120x1A8W1PSYSRESET_NFlush Control Register
Table 21-1130x1ACW1PSYSRESET_NMAC Statistics Clear Control Register
Table 21-114

n is 0 to 56

0x1B0 to
0x290RW-PRegisterPORESET_NI/O MUXCELL Configuration Register