21.4 Register Map

The following table lists all the registers in the SYSREG block. The SYSREG block is located at address 0x40038000 in Cortex-M3 processor address space.

Table 21-2. SYSREG
Register Name Addr.

Offset

 Register Type Flash Write Protect Reset Source Description
Table 21-4 0x0 RW-P Register SYSRESET_N Controls address mapping of the eSRAMs
Table 21-5 0x4 RW-P Register SYSRESET_N eSRAM0 and eSRAM1 maximum latency
Table 21-7 0x8 RW-P Register SYSRESET_N DDR Configuration Register
Table 21-8 0XC RW-P Register SYSRESET_N eNVM Configuration Register
Table 21-10 0x10 RW-P Register SYSRESET_N eNVM Remap Base Address Control Register
Table 21-11 0x14 RW-P Register SYSRESET_N eNVM Remap Base Address Control Register
Table 21-12 0x18 RW-P Register SYSRESET_N Used to configure cache
Table 21-13 0x1C RW-P Register SYSRESET_N Cache Region Control Register
Table 21-14 0x24 RW-P Register SYSRESET_N Cache Flush Index Control Register
Table 21-15 0x28 RW-P Register SYSRESET_N DDR write buffer timeout
Table 21-16 0x2C RW-P Register SYSRESET_N DDR non-bufferable address region base address
Table 21-17 0x30 RW-P Register SYSRESET_N Size of non- bufferable address region
Table 21-19 0x34 RW-P Register SYSRESET_N MSS DDR bridge Configuration Register
Table 21-20 0x38 RW-P Register SYSRESET_N EDAC Configuration Register for eSRAM0, eSRAM1, USB, MAC, and CAN
Table 21-21 0x3C RW-P Register SYSRESET_N Master Weight Configuration Register 0
Table 21-22 0x40 RW-P Register SYSRESET_N Master Weight Configuration Register 1
Table 21-24 0x44 RW-P Register SYSRESET_N Enables software interrupt
Table 21-25 0x48 RW-P Bit SYSRESET_N Software Reset Control Register
Table 21-26 0x4C RW-P Register SYSRESET_N Cortex M3 Configuration Register
Table 21-27 0x50 RW-P Register SYSRESET_N Controls fabric interface
Table 21-28 0x54 RW-P Register SYSRESET_N Controls MSS peripherals
Table 21-29 0x58 RW-P Register PORESET_N Configures GPIO system reset
Table 21-30 0x5C RW-P Register PORESET_N GPIO Input Source Select Control Register
Table 21-31 0x60 RW-P Register PORESET_N MDDR Configuration Register
Table 21-32 0x64 RW-P Register PORESET_N Configures USB data interfaces from IOMUXCELLs and I/O pads
Table 21-33 0x68 RW-P Register PORESET_N Peripheral Clock MUX Select Control Register
Table 21-34 0x6C RW-P Register PORESET_N Configures Watchdog timer
Table 21-35 0x70 RW-P Register PORESET_N MDDR I/O Calibration Control Register
Reserved 0x74
Table 21-36 0x78 RW-P Register SYSRESET_N Enables/disables 1-bit error, 2-bit error status for eSRAM0, eSRAM1, USB, CAN, and MAC
Table 21-37 0x7C RW-P Register SYSRESET_N Configures USB interface
Table 21-38 0x80 RW-P Register SYSRESET_N Controls the pipeline present in the memory read path of eSRAM memory
Table 21-39 0x84 RW-P Register SYSRESET_N MSS Interrupt Enable Control Register
Table 21-40 0x88 RW-P Register SYSRESET_N Configures RTC timer WAKEUP signal
Table 21-41 0x8C RW-P Register SYSRESET_N MAC Configuration Register
Table 21-42 0x90 RW-P Register CC_RESET_N Controls the configuration input of MPLL register
Table 21-44 0x94 RW-P Register CC_RESET_N Controls the configuration input of MPLL register
Table 21-45 0x98 RW-P Field CC_RESET_N MSS DDR bridge FACC1 Configuration Register
Table 21-47 0x9C RW-P Field CC_RESET_N MSS DDR bridge FACC2 Configuration Register
Table 21-48 0xA0 RW-P Register CC_RESET_N PPL Lock Enable Control Register
Table 21-49 0xA4 RW-P Register SYSRESET_N Starts FPGA fabric calibration test circuit
Table 21-50 0xA8 RW-P Register SYSRESET_N PLL Delay Line Select Control Register
Table 21-51 0xAC RW-P Register SYSRESET_N MAC status clear on read
Table 21-52 0xB0 RW Reset Source Control Register
Table 21-53 0xB4 RO SYSRESET_N Dcode Bus Error Address Status Register
Table 21-54 0xB8 RO SYSRESET_N Icode Bus Error Address Status Register
Table 21-55 0xBC RO SYSRESET_N System Bus Error Address Status Register
Reserved 0xC0 SYSRESET_N
Table 21-56 0xC4 RO SYSRESET_N ICode Miss Control Status Register
Table 21-57 0xC8 RO SYSRESET_N ICode Hit Control Status Register
Table 21-58 0xCC RO SYSRESET_N DCode Miss Control Status Register
Table 21-59 0xD0 RO SYSRESET_N DCode Hit Control Status Register
Table 21-60 0xD4 RO SYSRESET_N ICode Transaction Count Control Status Register
Table 21-61 0xD8 RO SYSRESET_N DCode Transaction count Control Status Register
Table 21-62 0xDC RO SYSRESET_N MSS DDR Bridge DS Master Error Address Status Register
Table 21-63 0xE0 RO SYSRESET_N MSS DDR Bridge High Performance DMA Master Error Address Status Register
Table 21-64 0xE4 RO SYSRESET_N MSS DDR Bridge AHB Bus Error Address Status Register
Table 21-65 0xE8 RO SYSRESET_N MSS DDR Bridge Buffer Empty Status Register
Table 21-66 0xEC RO SYSRESET_N MSS DDR Bridge Disable Buffer Status Register
Table 21-67 0xF0 RO SYSRESET_N 1-bit error and 2-bit error count of eSRAM0
Table 21-68 0xF4 RO SYSRESET_N 1-bit error and 2-bit error count of eSRAM1
Reserved 0xF8 SYSRESET_N
Table 21-69 0xFC RO SYSRESET_N 1-bit error and 2-bit error count of MAC transmitter
Table 21-70 0x100 RO SYSRESET_N 1-bit error and 2-bit error count of MAC receiver
Table 21-71 0x104 RO SYSRESET_N 1-bit error and 2-bit error count of USB
Table 21-72 0x108 RO SYSRESET_N 1-bit error and 2-bit error count of CAN
Table 21-73 0x10C RO SYSRESET_N Address from eSRAM0 on which 1-bit and 2-bit SECDED error has occurred
Table 21-74 0x110 RO SYSRESET_N Address from eSRAM1 on which 1-bit and 2-bit SECDED error has occurred
Table 21-75 0x114 RO SYSRESET_N Address from MAC receiver on which 1-bit and 2-bit SECDED error has occurred
Table 21-76 0x118 RO SYSRESET_N Address from MAC transmitter on which 1-bit and 2 bit SECDED error has occurred.
Table 21-77 0x11C RO SYSRESET_N Address from CAN on which 1-bit and 2-bit SECDED error has occurred
Table 21-78 0x120 RO SYSRESET_N Address from USB on which 1-bit and 2-bit SECDED error has occurred
Table 21-79 0x124 RO-U SYSRESET_N Read and write security for masters 0, 1, and 2 to eSRAM0, eSRAM1, eNVM1, eNVM0, and MSS DDR bridge
Table 21-80 0x128 RO-U SYSRESET_N Read and write security for masters 4, 5, and DDR_FIC to eSRAM0, eSRAM1, eNVM1, eNVM0, and MSS DDR bridge
Table 21-81 0x12C RO-U SYSRESET_N Read and write security for masters 3, 6, 7, and 8 to eSRAM0, eSRAM1, eNVM1, eNVM0, and MSS DDR bridge
Table 21-82 0x130 RO-U SYSRESET_N Read and write security for master 9 to eSRAM0, eSRAM1, eNVM1, eNVM0, and MSS DDR bridge
Table 21-83 0x134 RO SYSRESET_N Cortex-M3 processor Status Register
Table 21-84 0x138 RO SYSRESET_N ETM count for lower bits [31:0]
Table 21-85 0x13C RO SYSRESET_N ETM count for higher bits [47:32]
Table 21-86 0x140 RO SYSRESET_N Device Status Register
Table 21-87 0x144 RO-U SYSRESET_N Configuration for accessibility of protect regions of eNVM0 and eNVM1
Table 21-88 0x148 RO-U PORESET_N Code shadow Status Register
Table 21-89 0x14C RO Configures device version
Table 21-90 0x150 RO MSS DDR PLL Status Register
Table 21-91 0x154 RO SYSRESET_N USB Status Register
Table 21-92 0x158 RO SYSRESET_N Busy status eNVM0 and eNVM1
Reserved 0x15C
Table 21-93 0x160 RO SYSRESET_N MSS DDR bridges status
Table 21-94 0x164 RO PORESET_N DDR I/O Calibration Status Register
Table 21-95 0x168 RO SYSRESET_N MSS DDR Clock Calibration Status Register
Table 21-96 0x16C RO-P PORESET_N Configures Watchdog load value
Table 21-97 0x170 RO-P PORESET_N Configures Watchdog MVRP value
Table 21-98 0x174 RO-P SYSRESET_N User Configuration Register 0
Table 21-99 0x178 RO-P SYSRESET_N User Configuration Register 1
Table 21-100 0x17C RO-P SYSRESET_N User Configuration Register 2
Table 21-101 0x180 RO-P SYSRESET_N User Configuration Register 3
Table 21-102 0x184 RO-P SYSRESET_N Size of memory protected from fabric master
Table 21-104 0x188 RO-P SYSRESET_N Base address which is protected from fabric master
Table 21-105 0x18C RO-P SYSRESET_N MSS GPIO Definition Register
Table 21-106 0x190 SW1C SYSRESET_N Status of 1-bit SECDED error detection and correction, 2-bit SECDED error detection for eSRAM0, eSRAM1, MAC, USB, and CAN
Table 21-107 0x194 SW1C SYSRESET_N MSS Internal Status Register
Table 21-108 0x198 SW1C SYSRESET_N MSS External Status Register
Table 21-109 0x19C SW1C PORESET_N Watchdog Time out event register
Table 21-110 0x1A0 W1P SYSRESET_N Clear MSS counters
Table 21-111 0x1A4 W1P SYSRESET_N Clears 16-bit counter value in eSRAM0, eSRAM1, MAC, USB, and CAN corresponding to count value of EDAC 1-bit and 2-bit errors
Table 21-112 0x1A8 W1P SYSRESET_N Flush Control Register
Table 21-113 0x1AC W1P SYSRESET_N MAC Statistics Clear Control Register
Table 21-114

n is 0 to 56

 0x1B0 to
0x290 RW-P Register PORESET_N I/O MUXCELL Configuration Register