6.1.2 Timing Diagrams

The following figures are the functional timing diagrams for AHBL read/write transactions through the AHB bus matrix and AHB-to-AHB bridge. Signals to/from a master are denoted by X in the signal name, and signals to/from a slave are denoted with Y in the signal name. For example, if Cortex-M3 processor master initiates the transactions of read/write to the eSRAM slave then the signals with X in the signal name indicates the signals of the Cortex-M3 processor and signals with Y indicate slave eSRAM signals.

Figure 6-6. AHB-to-AHB Write Transactions

Figure 6-7. AHB-to-AHB Read Transactions

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