6.1.1 Architecture Overview

Figure 6-2 depicts the interconnection between the master stage blocks and the slave stage blocks. The basic building blocks of the AHB bus matrix are the master stage block with an address decoder and the slave stage block with a slave arbiter. Each master interfaces with the master stage block and each slave interfaces with the slave stage block. The masters and slaves connect as shown in Figure 6-1.

An address decoder sub-block in each master stage generates the slave select signal to the corresponding slave. A slave arbiter sub-block in each slave stage generates the address-ready signal to the selected master.

Table 6-1. AHB Bus Matrix Connectivity
			Masters
			M3  DCode Bus	M3 ICode Bus	M3 System Bus	System Controller	HPDMA	FIC_0	FIC_1	MAC	PDMA	USB
			MM1	MM0	MM2	MM9	MM3	MM4	MM5	MM6	MM7	MM8
Priority			1	2	3	4	4	4	4	4	4	4
Arbitration			Fixed	Fixed	Fixed	Fixed	WRR	WRR	WRR	WRR	WRR	WRR
Slaves	eSRAM0	MS0	RW	RW	RW	RW	RW	RW	RW	RW	RW	RW
	eSRAM1	MS1	RW	RW	RW	RW	RW	RW	RW	RW	RW	RW
	eNVM_0	MS2	RW¹	R¹	RW¹	RW¹	R¹	RW¹	RW¹	—	RW¹	—
	eNVM_1	MS3	RW¹	R¹	RW¹	RW¹	R¹	RW¹	RW¹	—	RW¹	—
	FIC_0	MS4	—	—	RW	RW	RW	RW	RW	RW	RW	RW
	MAC	MS5	—	—	RW	RW	—	RW	RW	—	—	—
	FIC_1		—	—	RW	RW	RW	RW	RW	RW	RW	RW
	SYSREG		—	—	RW	RW	—	RW	RW	—	—	—
	APB_0		—		RW	RW	—	RW	RW	—	RW	—
	APB_1		—		RW	RW	—	RW	RW	—	RW	—
	APB_2		—		RW	RW	—	RW	RW	—	—	—
	USB		—		RW	RW	—	RW	RW	—	—	—
	MSS DDR Bridge	MS6	—		—	RW	—	RW	RW	RW	RW	RW

Note:

Exercise caution while commanding the eNVM to program data. Other masters in the system may not be aware that the eNVM is unavailable if it is in a program cycle. Microchip recommends you use some form of software semaphore to control access.
Low numbers in priority represent higher priority, with 1 being the highest priority.

Reads or writes to areas not allowed cause the AHB bus matrix to complete the transaction with an HRESP error indication. An error bit is set in the SW_ERRORSTATUS field of the MSS_EXTERNAL_SR register. The following types of errors can occur:

Write by an enabled master to a slave that is not RW
Write by an enabled master to addresses not corresponding to a slave
Write by the fabric master to the protected region
Write by a disabled master to any location
Read by an enabled master to any slave that is not R or RW
Read by an enabled master to addresses not corresponding to a slave
Read by the fabric master to the protected region
Read by a disabled master to any location

Figure 6-2. Master Stage and Slave Stage Interconnection

To reduce the load on the AHB bus matrix, some of the low-performance peripherals are connected through the synchronous AHB-to-AHB bridge with an address decoder. The AHB bus matrix is constructed of combinatorial logic, except for the AHB-to-AHB bridge, which inserts a one-cycle delay in each direction.

The following figure shows the block diagram of all the APB peripherals connected to AHB bus matrix using the AHB-to-AHB bridge. The MSS APB peripherals are connected through the AHB to APB bus.

Figure 6-3. Block Diagram of APB Destinations Connected to AHB Bus Matrix