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SmartFusion 2 Microcontroller Subsystem
SmartFusion 2 Microcontroller Subsystem
  1. Home
  2. 2 Cortex-M3 Processor (Reference Material)
  3. 2.5 Cortex-M3 Processor Description
  4. 2.5.2 Memory Model
  5. 2.5.2.5 Bit-Banding
  6. 2.5.2.5.2 Directly accessing a bit-band region
  • Introduction
  • 1 Cortex-M3 Processor Overview and Debug Features
  • 2 Cortex-M3 Processor (Reference Material)
    • 2.1 System Level Interface
    • 2.2 Integrated Configurable Debug
    • 2.3 Cortex-M3 Processor Features and Benefits Summary
    • 2.4 Cortex-M3 Processor Core Peripherals
    • 2.5 Cortex-M3 Processor Description
      • 2.5.1 Programmers Model
      • 2.5.2 Memory Model
        • 2.5.2.1 Memory Regions, Types and Attributes
        • 2.5.2.2 Memory System Ordering of Memory Accesses
        • 2.5.2.3 Behavior of Memory Accesses
        • 2.5.2.4 Software Ordering of Memory Accesses
        • 2.5.2.5 Bit-Banding
          • 2.5.2.5.1 Directly Accessing an Alias Region
          • 2.5.2.5.2 Directly accessing a bit-band region
        • 2.5.2.6 Memory Endianness
        • 2.5.2.7 Synchronization Primitives
        • 2.5.2.8 Programming Hints for the Synchronization Primitives
      • 2.5.3 Exception Model
      • 2.5.4 Fault Handling
      • 2.5.5 Power Management
    • 2.6 Cortex-M3 Processor Instruction Set
    • 2.7 Cortex-M3 Processor Peripherals
  • 3 Cache Controller
  • 4 Embedded NVM (eNVM) Controllers
  • 5 Embedded SRAM (eSRAM) Controllers
  • 6 AHB Bus Matrix
  • 7 High Performance DMA Controller
  • 8 Peripheral DMA
  • 9 Universal Serial Bus On-The-Go Controller
  • 10 Ethernet MAC
  • 11 CAN Controller
  • 12 MMUART Peripherals
  • 13 Serial Peripheral Interface Controller
  • 14 Inter-Integrated Circuit Peripherals
  • 15 MSS GPIO
  • 16 Communication Block
  • 17 RTC System
  • 18 System Timer
  • 19 Watchdog Timer
  • 20 Reset Controller
  • 21 System Register Block
  • 22 Fabric Interface Interrupt Controller
  • 23 Fabric Interface Controller
  • 24 APB Configuration Interface
  • 25 Error Detection and Correction Controllers
  • 26 Revision History
  • Microchip FPGA Support
  • Microchip Information

2.5.2.5.2 Directly accessing a bit-band region

2.5.2.3 Behavior of Memory Accesses describes the behavior of direct byte, halfword, or word accesses to the bit-band regions.

The online versions of the documents are provided as a courtesy. Verify all content and data in the device’s PDF documentation found on the device product page.

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