22.5 FIIC Controller Register Bit Definitions
The following tables provide the bit definitions for registers in the FIIC.
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| 0 | SPIINT0_ENBL | 0 | SPIINT0 interrupt from the MSS SPI_0 block to fabric. 1: Enable 0: Mask |
| 1 | SPIINT1_ENBL | 0 | SPIINT1 interrupt from the MSS SPI_1 block to fabric. 1: Enable 0: Mask |
| 2 | I2C_INT0_ENBL | 0 | I2C_INT0 interrupt from the MSS I2C_0 block to fabric. 1: Enable 0: Mask |
| 3 | I2C_INT1_ENBL | 0 | I2C_INT1 interrupt from the MSS I2C_1 block to fabric. 1: Enable 0: Mask |
| 4 | MMUART0_INTR_ENBL | 0 | MMUART0_INTR interrupt from the MSS MMUART_0 block to fabric. 1: Enable 0: Mask |
| 5 | MMUART1_INTR_ENBL | 0 | MMUART1_INTR interrupt from the MSS MMUART_1 block to fabric. 1: Enable 0: Mask |
| 6 | MAC_INT_ENBL | 0 | MAC_INT interrupt from the MSS Ethernet MAC block to fabric. 1: Enable 0: Mask |
| 7 | USB_MC_INT_ENBL | 0 | USB_MC_INT interrupt from the MSS USB block to fabric. 1: Enable 0: Mask |
| 8 | PDMAINTERRUPT_ENBL | 0 | PDMAINTERRUPT interrupt from the MSS peripheral DMA block to fabric. 1: Enable 0: Mask |
| 9 | HPD_XFR_CMP_INT_ENBL | 0 | HPD_XFR_CMP_INT interrupt from the MSS HPDMA block to fabric. 1: Enable 0: Mask |
| 10 | TIMER1_INTR_ENBL | 0 | TIMER1_INTR interrupt from the MSS TIMER1 block to fabric. 1: Enable 0: Mask |
| 11 | TIMER2_INTR_ENBL | 0 | TIMER2_INTR interrupt from the MSS TIMER2 block to fabric. 1: Enable 0: Mask |
| 12 | CAN_INTR_ENBL | 0 | CAN_INTR interrupt from the MSS CAN controller block to fabric. 1: Enable 0: Mask |
| 13 | RTC_WAKEUP_INTR_ENBL | 0 | RTC_WAKEUP_INTR interrupt from the MSS RTC block to fabric. 1: Enable 0: Mask |
| 14 | WDOGWAKEUPINT_ENBL | 0 | WDOGWAKEUPINT interrupt from the MSS Watchdog block to fabric.
The watchdog is refreshed by writing to the WDOGREFRESH register. When the counter value is greater than the value in the WDOGMVRP register and SLEEPING input to the watchdog is asserted, the WDOGWAKEUPINT interrupt is generated. |
| 15 | MSSDDR_PLL_LOCKLOST_INT _ENBL | 0 | MSSDDR_PLL_LOCKLOST_INT interrupt from MPLL to the fabric. 1: Enable 0: Mask |
| 16 | ENVM_INT0_ENBL | 0 | ENVM_INT0 interrupt from the MSS ENVM0 block to fabric. 1: Enable 0: Mask |
| 17 | ENVM_INT1_ENBL | 0 | ENVM_INT1 interrupt from MSS ENVM1 block to fabric. 1: Enable 0: Mask |
| 18 | I2C_SMBALERT0_ENBL | 0 | I2C_SMBALERT0 interrupt from MSS I2C_0 block to fabric. 1: Enable 0: Mask |
| 19 | I2C_SMBSUS0_ENBL | 0 | I2C_SMBSUS0 interrupt from the MSS I2C_0 block to fabric. 1: Enable 0: Mask |
| 20 | I2C_SMBALERT1_ENBL | 0 | I2C_SMBALERT1 interrupt from the MSS I2C_1 block to fabric. 1: Enable 0: Mask |
| 21 | I2C_SMBSUS1_ENBL | 0 | I2C_SMBSUS1 interrupt from the MSS I2C_1 block to fabric. 1: Enable 0: Mask |
| 22 | HPD_XFR_ERR_INT_ENBL | 0 | HPD_XFR_ERR_INT interrupt from the MSS HPDMA block to fabric. 1: Enable 0: Mask |
| 23 | MSSDDR_PLL_LOCK_INT_ENBL | 0 | MSSDDR_PLL_LOCK_INT interrupt from the MPLL block to fabric. 1: Enable 0: Mask |
| 24 | SW_ERRORINTERRUPT_ENBL | 0 | SW_ERRORINTERRUPT interrupt from the SYSREG block to fabric. 1: Enable 0: Mask HRESP from AHB bus Matrix assertion to the master in case of blocked fabric master or for the unimplemented address space results in SW_ERRORINTERRUPT signal. In case of above error condition the following signals are ORed together in SYSREG to create the SW_ERRORINTERRUPT signal: 1. HRESP assertion being issued to the HPDMA. 2. HRESP assertion being issued to FIC_0. 3. HRESP assertion being issued to FIC_1. 4. HRESP assertion being issued to the Ethernet MAC. 5. HRESP assertion being issued to the peripheral DMA engine. 6. HRESP assertion being issued to the USB. 7. HRESP assertion being issued to the system controller. |
| 25 | DDRB_INTR_ENBL | 0 | MSS DDR bridge DDRB_INTR to fabric. 1: Enable 0: Mask DDRB_INTR input indicates that any one of the following interrupts are asserted from the MSS DDR bridge: DDRB_ERROR interrupts DDRB_DISABLEDONE interrupts DDRB_LOCKTIMEOUT interrupts |
| 26 | ECCINTR_ENBL | 0 | ECCINTR interrupt from ESRAM0, ESRAM1 CAN, MDDR, and USB to fabric.
The ECCINTR interrupt is asserted when an SECDED error has been detected in ESRAM0, ESRAM1, CAN, MDDR, or USB memories. |
| 27 | CACHE_ERRINTR_ENBL | 0 | CACHE_ERRINTR interrupt from the cache controller block to fabric. 1: Enable 0: Mask The CACHE_ERRINTR interrupt is generated in the SYSREG block by ORing of the following interrupts from the SmartFusion 2 SoC FPGA CACHE block: CC_HRESPERRINT0 CC_HRESPERRINT1 CC_HRESPERRINT2 CC_HRESPERRINT3 CC_EDCERRINT |
| 28 | SOFTINTERRUPT_ENBL | 0 | SOFTINTERRUPT interrupt from the SYSREG block to fabric. 1: Enable 0: Mask SOFTINTERRUPT is set by the Cortex-M3 processor firmware by writing to the soft interrupt SYSREG block bits. |
| 29 | COMBLK_INTR_ENBL | 0 | COMBLK_INTR interrupt from the COMM_BLK block to fabric. 1: Enable 0: Mask |
| 30 | USB_DMA_INT_ENBL | 0 | USB_DMA_INT interrupt from USB’s DMA controller to fabric. 1: Enable 0: Mask |
| 31 | Reserved | 0 | Reserved |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| 0 | Reserved | 0 | Reserved |
| 1 | Reserved | 0 | Reserved |
| 2 | Reserved | 0 | Reserved |
| 3 | MDDR_IO_CALIB_INT_ENBL | 0 | MDDR_IO_CALIB_INT interrupt from the MDDR block to fabric. 1: Enable 0: Mask |
| 4 | Reserved | 0 | Reserved |
| 5 | FAB_PLL_LOCK_INT_ENBL | 0 | FAB_PLL_LOCK_INT interrupt from FAB_PLL. 1: Enable 0: Mask |
| 6 | FAB_PLL_LOCKLOST_INT_ENBL | 0 | FAB_PLL_LOCKLOST_INT interrupt from FAB_PLL. 1: Enable 0: Mask |
| 7 | FIC64_INT_ENBL | 0 | FIC64_INT interrupt from the DDR_FIC block. 1: Enable 0: Mask |
| 8-31 | Reserved | 0 | Reserved |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| 0 | Reserved | 0 | Reserved |
| 1 | Reserved | 0 | Reserved |
| 2 | Reserved | 0 | Reserved |
| 3 | MDDR_IO_CALIB_INT_STATUS | 0 | Set if the interrupt source for MDDR_IO_CALIB_INT is asserted and the MDDR_IO_CALIB_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE1 is High. |
| 4 | Reserved | 0 | Reserved |
| 5 | FAB_PLL_LOCK_INT_STATUS | 0 | Set if the interrupt source for FAB_PLL_LOCK_INT is asserted and the FAB_PLL_LOCK_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE1 is High. |
| 6 | FAB_PLL_LOCKLOST_INT_STATUS | 0 | Set if the interrupt source for FAB_PLL_LOCKLOST_INT is asserted and the FAB_PLL_LOCKLOST_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE1 is High. |
| 7 | FIC64_INT_STATUS | 0 | Set if the interrupt source for FIC64_INT is asserted and the FIC64_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE1 is High. |
| 8-31 | Reserved | 0 | Reserved |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| 0 | SPIINT0_STATUS | 0 | Set if the interrupt source for SPIINT0 is asserted and the SPIINT0_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 1 | SPIINT1_STATUS | 0 | Set if the interrupt source for SPIINT1 is asserted and the SPIINT1_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 2 | I2C_INT0_STATUS | 0 | Set if the interrupt source for I2C_INT0 is asserted and the I2C_INT0_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 3 | I2C_INT1_STATUS | 0 | Set if the interrupt source forI2C_INT1 is asserted and the I2C_INT1_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 4 | MMUART0_INTR_STATUS | 0 | Set if the interrupt source for MMUART0_INTR is asserted and the MMUART0_INTR_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 5 | MMUART1_INTR_STATUS | 0 | Set if the interrupt source for MMUART1_INTR is asserted and the MMUART1_INTR_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 6 | MAC_INT_STATUS | 0 | Set if the interrupt source for MAC_INT is asserted and the MAC_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 7 | USB_MC_INT_STATUS | 0 | Set if the interrupt source for USB_MC_INT is asserted and the USB_MC_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 8 | PDMAINTERRUPT_STATUS | 0 | Set if the interrupt source for PDMAINTERRUPT is asserted and the PDMAINTERRUPT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 9 | HPD_XFR_CMP_INT_STATUS | 0 | Set if the interrupt source for HPD_XFR_CMP_INT is asserted and the HPD_XFR_CMP_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 10 | TIMER1_INTR_STATUS | 0 | Set if the interrupt source for TIMER1_INTR is asserted and the TIMER1_INTR_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 11 | TIMER2_INTR_STATUS | 0 | Set if the interrupt source for TIMER2_INTR is asserted and the TIMER2_INTR_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 12 | CAN_INTR_STATUS | 0 | Set if the interrupt source for CAN_INTR is asserted and the CAN_INTR_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 13 | RTC_WAKEUP_INTR_STATUS | 0 | Set if the interrupt source for RTC_WAKEUP_INTR is asserted and the RTC_WAKEUP_INTR_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 14 | WDOGWAKEUPINT_STATUS | 0 | Set if the interrupt source for WDOGWAKEUPINT is asserted and the WDOGWAKEUPINT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 15 | MSSDDR_PLL_LOCKLOST_INT_STATUS | 0 | Set if the interrupt source for MSSDDR_PLL_LOCKLOST_INT is asserted and the MSSDDR_PLL_LOCKLOST_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 16 | ENVM_INT0_STATUS | 0 | Set if the interrupt source for ENVM_INT0 is asserted and the ENVM_INT0_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 17 | ENVM_INT1_STATUS | 0 | Set if the interrupt source for ENVM_INT1 is asserted and the ENVM_INT1_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 18 | I2C_SMBALERT0_STATUS | 0 | Set if the interrupt source for I2C_SMBALERT0 is asserted and the I2C_SMBALERT0_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 19 | I2C_SMBSUS0_STATUS | 0 | Set if the interrupt source for I2C_SMBSUS0 is asserted and the I2C_SMBSUS0_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 20 | I2C_SMBALERT1_STATUS | 0 | Set if the interrupt source for I2C_SMBALERT1 is asserted and the I2C_SMBALERT1_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 21 | I2C_SMBSUS1_STATUS | 0 | Set if the interrupt source for I2C_SMBSUS1 is asserted and the I2C_SMBSUS1_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 22 | HPD_XFR_ERR_INT_STATUS | 0 | Set if the interrupt source for HPD_XFR_ERR_INT is asserted and the HPD_XFR_ERR_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 23 | MSSDDR_PLL_LOCK_INT_STATUS | 0 | Set if the interrupt source for MSSDDR_PLL_LOCK_INT is asserted and the MSSDDR_PLL_LOCK_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. MSSDDR_PLL_LOCK_INT interrupt is asserted when MPLL achieves lock. |
| 24 | SW_ERRORINTERRUPT_STATUS | 0 | Set if the interrupt source for SW_ERRORINTERRUPT is asserted and the SW_ERRORINTERRUPT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 25 | DDRB_INTR_STATUS | 0 | Set if the interrupt source for DDRB_INTR is asserted and the DDRB_INTR_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 26 | ECCINTR_STATUS | 0 | Set if the interrupt source for ECCINTR is asserted and the ECCINTR_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 27 | CACHE_ERRINTR_STATUS | 0 | Set if the interrupt source for CACHE_ERRINTR is asserted and the CACHE_ERRINTR_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 28 | SOFTINTERRUPT_STATUS | 0 | Set if the interrupt source for SOFTINTERRUPT is asserted and the SOFTINTERRUPT_ENBL interrupt enable bit inINTERRUPT_ENABLE0 is High. |
| 29 | COMBLK_INTR_STATUS | 0 | Set if the interrupt source for COMBLK_INTR is asserted and the COMBLK_INTR_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 30 | USB_DMA_INT_STATUS | 0 | Set if the interrupt source for USB_DMA_INT is asserted and USB_DMA_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. |
| 31 | Reserved | 0 | Reserved |
| Bit Number | Name | Reset Value | Description |
|---|---|---|---|
| 0 | SELECT_MODE | 0 | The following are the valid values for this bit: 0: Select group 0 1: Select group 1 |
| 31:1 | Reserved | 0 | Reserved |