22.4 FIIC Controller Registers
The register set contains two interrupt enable registers, two interrupt status registers and an interrupt mode register. The interrupt enable registers do not affect the Cortex-M3 processor NVIC; these are per bit enables of the interrupt routed to the FPGA fabric.
The following table summarizes each of the registers covered by this chapter. The base address of the FIIC block is 0x40006000.
| Register Name | Address Offset | Register Type | Reset Value | Description |
|---|---|---|---|---|
| Table 22-7 | 0x00 | R/W | 0x0 | Enables MSS to fabric interrupts |
| Table 22-8 | 0x04 | R/W | 0x0 | Enables MSS to fabric interrupts |
| Table 22-10 | 0x08 | RO | 0x0 | Indicates which interrupts are active |
| Table 22-9 | 0x0C | RO | 0x0 | Indicates which interrupts are active |
| Table 22-11 | 0x10 | R/W | 0x0 | Indicates select group 0 or select group1 |