24.1.1 Architecture Overview

The preceding figure shows the APB configuration interfaces and SERDES and DDR subsystems connectivity with the MSS master. The AHB bus matrix FIC_2 port routes the APB configuration interface to the FPGA fabric. The SERDES and DDR subsystems are connected through CoreSF2Config soft IP. CoreSF2Config must be instantiated (available in the Libero SoC IP Catalog) in the FPGA fabric to allow configuration of FDDR, SERDESIF, and MDDR.

The following tables list the APB configuration interface signals and descriptions.

The APB configuration space is divided into multiple partitions; each partition is reserved to one specific module or type of functionality. The APB addresses are word-aligned.

The base address of FDDR, SERDESIF0, and SERDESIF1 configuration address space resides at 0x40020400 and extends to address 0x4002FFFF in the memory map of the Cortex-M3 processor on the AHB bus matrix.

• Refer to the “Fabric Double Data Rate Subsystem” chapter in the UG0446: SmartFusion2 and IGLOO2 FPGA High Speed DDR Interfaces User Guide for FDDR register map details and address space partition.
• Refer to the “Serializer/Deserializer” chapter in the UG0447: SmartFusion2 and IGLOO2 FPGA High Speed Serial Interfaces User Guide for SERDES register map details and address space partition.

  The base address of the MDDR configuration address space resides at 0x40020000 and extends to address 0x400203FF in the memory map of the Cortex-M3 processor on the AHB bus matrix.

• Refer to the “MSS DDR Subsystem” chapter in the UG0446: SmartFusion2 and IGLOO2 FPGA High Speed DDR Interfaces User Guide for MDDR register map details and address space partition.