2.5.2.3.1 Additional memory access constraints for caches and shared memory

When a system includes caches or shared memory, some memory regions have additional access constraints, and some regions are subdivided, as detailed in the following table.

Table 2-12. Memory Region Shareability and Cache Policies
Address rangeMemory regionMemory type1ShareabilityCache policy2
0x00000000- 0x1FFFFFFFCodeNormal—WT
0x20000000- 0x3FFFFFFFSRAMNormal—WBWA
0x40000000- 0x5FFFFFFFPeripheralDevice——
0x60000000- 0x7FFFFFFFExternal RAMNormal—WBWA
0x80000000- 0x9FFFFFFFWT
0xA0000000- 0xBFFFFFFFExternal deviceDeviceShareable—
0xC0000000- 0xDFFFFFFFNon-shareable
0xE0000000- 0xE00FFFFFPrivate Peripheral BusStrongly- orderedShareable—
0xE0100000- 0xFFFFFFFFVendor-specific deviceDevice——
Note:
  1. See Memory Regions, Types and Attributes for more information.
  2. WT = Write through, no write allocate. WBWA = Write back, write allocate.