2.5.2.3.1 Additional memory access constraints for caches and shared memory

When a system includes caches or shared memory, some memory regions have additional access constraints, and some regions are subdivided, as detailed in the following table.

Table 2-12. Memory Region Shareability and Cache Policies
Address range	Memory region	Memory type¹	Shareability	Cache policy²
0x00000000- 0x1FFFFFFF	Code	Normal	—	WT
0x20000000- 0x3FFFFFFF	SRAM	Normal	—	WBWA
0x40000000- 0x5FFFFFFF	Peripheral	Device	—	—
0x60000000- 0x7FFFFFFF	External RAM	Normal	—	WBWA
0x80000000- 0x9FFFFFFF	External RAM	Normal	—	WT
0xA0000000- 0xBFFFFFFF	External device	Device	Shareable	—
0xC0000000- 0xDFFFFFFF	External device	Device	Non-shareable	—
0xE0000000- 0xE00FFFFF	Private Peripheral Bus	Strongly- ordered	Shareable	—
0xE0100000- 0xFFFFFFFF	Vendor-specific device	Device	—	—

Note:

See 2.5.2.1 Memory Regions, Types and Attributes for more information.
WT = Write through, no write allocate. WBWA = Write back, write allocate.