19.5 SYSREG Control Registers
In addition to the specific watchdog timer registers mentioned in Table 19-3, the registers mentioned in the following table also control the behavior of the watchdog timer. These registers are located in the System Register Block and are listed here for clarity. Refer to the SYSREG section of 19 Watchdog Timer for a detailed description of each register and bit.
| Register Name | Register Type | Flash Write Protect | Reset Source | Description |
|---|---|---|---|---|
| WDOG_CR | RW-P | Register | Poreset_n | Bit 0 of this register is WDOGENABLE.This goes as the Enable bit for the watchdog timer module. The status of this bit can be monitored in the WDOGENABLE register. Bit 1of this register is WDOGMODE. This bit is Reset/Interrupt mode selection bit from the system register. This value can be read from the WDOGCONTROL register within the watchdog timer module. |
| WDOGLOAD | RO-P | Poreset_n | Bits [25:0] of this register contain the upper 26-bits of the WDOGLOAD value register. | |
| WDOGMVRP | RO-P | Poreset_n | This register contains the WDOGMVRP value. |
Note: Register Types RW-P, RO-P are explained in 19 Watchdog Timer.