19.1 Features

The watchdog timer has following features:

  • A 32-bit timer counts down from a preset value to zero, then performs one of the following user-configurable operations: If the counter is not refreshed, it will time out and either cause a system reset or generate an interrupt to the processor.
  • The watchdog timer counter is halted when the Cortex-M3 processor enters the debug state.
  • The watchdog timer can be configured to generate a wake up interrupt when the Cortex-M3 is in sleep mode.

As shown in the following figure, the watchdog timer is connected to the AHB bus matrix through the APB_0 interface.

Figure 19-1. Microcontroller Subsystem Showing Watchdog Timer