19.4 Watchdog Timer Register Map
The following table summarizes the watchdog timer register interface. Detailed description of the registers is given in Watchdog Timer Configuration Register Bit Definitions. The base address for the register details resides at 0x40005000 and extends to the address 0x40005FFF in the Cortex-M3 processor memory map.
| Register Name | Address Offset | R/W | Reset Source | Description |
|---|---|---|---|---|
| Table 19-4 | 0x00 | R | WDOGLOAD | Current value of the counter This register is reset with the value in the WDOGLOAD system register. |
| Table 19-5 | 0x04 | R | WDOGLOAD | Load value for the counter This register is reset with the value in the WDOGLOAD system register. |
| Table 19-6 | 0x08 | R | WDOGMVRP | Maximum value for which refreshing is permitted. This register is reset with the value in the WDOGMVRP system register. |
| Table 19-7 | 0x0C | W | N/A | Writing the value 0xAC15DE42 to this register causes the counter to be updated with the value in the WDOGLOAD register. |
| Table 19-8 | 0x10 | R | WDOGENABLE | Watchdog timer enables register This register is reset with the value in the WDOGENABLE bit in the WDOG_CR system register. |
| Table 19-9 | 0x14 | R/W | [31:3] and [1:0]=0X0 | Control register Bit 2 of this register is reset with the value of the WDOGMODE bit in the WDOG_CR system register. |
| Bit 2=WDOGMODE | ||||
| Table 19-10 | 0x18 | R | 0X0 | Status register |
| Table 19-11 | 0x1C | R/W | 0X0 | Raw interrupt status |