9.2.2.2 UTMI+ (USB 2.0 Transceiver Macrocell Interface+) Interface
This is the external interface connecting the SmartFusion 2 USB OTG controller to an off-chip UTMI PHY device. For UTMI interface, all the interface signals are routed through the FPGA fabric on to the MSIOs.
| Signal Name | Direction | Description |
|---|---|---|
| UTMI_SUSPENDM | Out | Indicates asynchronous Suspend mode (derived from signals from both CLK and XCLK flip-flops). When enabled through bit 0 of the Power register, goes low when the device is in Suspend mode. Otherwise high (intended to drive a UTMI PHY). |
| UTMI_LINESTATE[1:0] | In | Shows the current state of single-ended
receivers. LINESTATE[0] reflects the state of D+; LINESTATE[1] reflects state
of D-. 00: SE0 01: J State 10: K State 11: SE1 |
| UTMI_OPMODE[1:0] | Out | Selects Operating mode 00: Normal operation 01: Non-driving 10: Bit stuffing and NRZI encoding disabled 11: Reserved |
| UTMI_XDATAIN[7:0] | In | Received data |
| UTMI_XDATAOUT[7:0] | Out | Data to be transmitted |
| UTMI_TXVALID | Out | Transmit data valid. Indicates that valid data has been transmitted. |
| UTMI_TXREADY | In | Transmit data ready. Indicates that the transmitter requires data. |
| UTMI_RXVALID | In | Receive data valid. Indicates that valid data has been received. |
| UTMI_RXACTIVE | In | Indicates that a valid packet is being received. |
| UTMI_RXERROR | In | Indicates that the received packet is about to be aborted due to an error. |
| UTMI_XCVRSEL[1:0] | Out | Transceiver select
|
| UTMI_TERMSEL | Out | Termination select.
May be used to switch the pull-up resistor on D+ |
| UTMI_VBUSVALID | In | Compares VBus to selected VBus valid
threshold (required to be between 4.4V and 4.75V)
|
| UTMI_AVALID | In | Compares VBus to session valid threshold for
a B device (required to be between 0.8V and 2V)
|
| UTMI_SESSEND | In | Compares VBus to session end threshold
(required to be between 0.2 V and 0.8 V)
|
| UTMI_SESSEND | In | Compares VBus to session end threshold
(required to be between 0.2V and 0.8V)
|
| UTMI_DRVVBUS | Out | Enables VBus power (used when the USB controller operates as an A device) |
| UTMI_CHRGVBUS | Out | Charges VBus (used during session request when the USB controller operates as a B device) |
| UTMI_DISCHRGVBUS | Out | Discharges VBus (used by B devices to ensure that the VBus is low enough before starting a session request protocol (SRP)) |
| UTMI_HOSTDISCON | In | Host mode only; must be asserted when a high
speed disconnect occurs (in accordance with the UTMI+ specification). Full/low speed connections are monitored through the LINESTATE signal. |
| UTMI_DPPULLDOWN | Out | Enables a pull-down resistor within the
transceiver on the D+ line
|
| UTMI_DMPULLDOWN | Out | Enables a pull-down resistor within the transceiver on the D– line. Needs to be high, when the USB controller is used for point-to-point communications. |
| UTMI_IDDIG | In | Indicates USB controller connector type. High = B-type, Low = A-type. |
| UTMI_IDPULLUP | Out | Enables for IDDIG signal generation |
| UTMI_VSTATUS[7:0] | In | PHY status data; 8-bit wide as per UTMI+ specifications |
| UTMI_VCONTROL[3:0] | Out | PHY control data; 8-bit wide as per UTMI+ specifications |
| UTMI_VCONTROLLOADM | Out | Active-low signal; asserted when new control information is required to be read – if implemented |
| UTMI_RXVALIDH | In | Tied permanently low at the fabric interface |
UTMI+Level3 signals are routed through the FPGA fabric onto MSIOs.
Important: The FPGA fabric design must implement a 'AND' logic
between UTMI_TXVALID and UTMI_TXREADY for proper data transmission.
For more information on USB 2.0 PHY interfaces refer to the following links: