25.3 How to Use EDAC

EDAC can be configured using the SECDED configurator available in the SmartFusion 2 SoC, as shown in the following figure. Using the SECDED configurator, EDAC options for the following memories can be configured:

  • eSRAM (eSRAM0, eSRAM1)
  • Ethernet MAC transmit and receive memory
  • USB internal memory
  • CAN internal memory
  • MDDR
Figure 25-3. EDAC in Read Mode (Reading From Memory)

The following figure shows the SECDED configurator options GUI available in the MSS. The SECDED configurator dialog box is organized as follows:

  • EDAC_ERROR BUS: This is the EDAC_ERROR bus signal to the FPGA fabric. This signal can be used to expose the error bus to the fabric for monitoring.
  • EDAC_ENABLE: EDAC_ENABLE can be used to enable the EDAC functionality for each of the following blocks: eSRAM0, eSRAM1, Ethernet MAC Tx and Rx RAMS, USB, CAN, and MDDR.
  • Enable EDAC Interrupt(s): Enable EDAC Interrupt(s) can be used to enable the interrupts for each of the following blocks: eSRAM0, eSRAM1, Ethernet MAC TX and RX RAMs, USB, and CAN. Selection options for enable interrupts are available as follows:
    • None
    • 1-bit error
    • 2-bit error
    • 1-bit and 2-bit errors
  • Enable MDDR ECC Interrupt: Enable MDDR ECC Interrupt can be used to enable the MSS DDR (MDDR) ECC interrupts.
Figure 25-4. EDAC in Read Mode (Reading From Memory)

The values entered in the configurator are exported into the programming files for programming the Flash bits that control the EDAC functionality. The Flash bits are loaded in the system registers at power-up (or when the DEVRST_N external pad is asserted/deasserted).