25.2 Configuration

The EDAC architecture is implemented to protect different types of memories. The data and checksum bit widths of the EDAC change according to the memory specifications.

Refer to the following chapters for EDAC configurations for specific types of memories:

• eSRAM: Embedded SRAM (eSRAM) Controllers
• Internal FIFOs of the Ethernet MAC: Ethernet MAC
• USB internal memory: Universal Serial Bus OTG Controller
• Internal RAM of the CAN controller: CAN Controller
• eNVM: Embedded Nonvolatile Memory (eNVM) Controllers

In the UG0446: SmartFusion2 and IGLOO2 FPGA High Speed DDR Interfaces User Guide, refer to the following chapters:

• MDDR: MDDR Subsystem
• FDDR: Fabric DDR Subsystem