7.1 Features

  • Faster read/write operations with two concurrent AHB masters
  • 32-bit AHB operation at 200 MHz
  • 32-bit APB slave interface for control and status registers at 25/50/100/200 MHz
  • Internal 32-bit control, status, and debug registers
  • Single DMA channel with four queuing HPDMA descriptors, serviced with round robin priority
  • Up to 64 KB data transfer in single channel request
  • 32-byte internal data buffer
  • Supports word aligned data transfers
  • Interrupts for DMA transfer complete and transfer errors
  • DMA transfer pause
  • Individual descriptor reset
  • Data transfer in little-endian format