7.4 HPDMA Controller Register Map

The following table summarizes the HPDMA controller register map. The sections that follow detail register bit descriptions of status, configuration, and debug registers. All the register bits are active high; on reset they assume default values. Register R/W corresponds to external processor accessibility. The address range of the HPDMA APB registers is x40014000 to x40014FFF. Only the 7 LSBs are considered for addressing the registers.

Table 7-2. HPDMA Register Map
Register Name	Address Offset	Register Type	Reset Value	Description
Table 7-3	x00	R	x0F	HPDMA Empty Descriptor register
Table 7-4	x04	R/W	x00	Descriptor 0 source memory start address
Table 7-8	x08	R/W	x00	Descriptor 0 destination memory start address
Table 7-12	x0C	R/W	x00	Descriptor 0 Control register
Table 7-16	x10	R	x00	Descriptor 0 Status register
Table 7-20	x14	R	x00	Descriptor 0 Pending Transfer register
Table 7-5	x18	R/W	x00	Descriptor 1 source memory start address
Table 7-9	x1C	R/W	x00	Descriptor 1 destination memory start address.
Table 7-13	x20	R/W	x00	Descriptor 1 Control register
Table 7-17	x24	R	x00	Descriptor 1 Status register
Table 7-21	x28	R	x00	Descriptor 1 Pending Transfer register
Table 7-6	x2C	R/W	x00	Descriptor 2 source memory start address
Table 7-10	x30	R/W	x00	Descriptor 2 destination memory start address
Table 7-14	x34	R/W	x00	Descriptor 2 Control register
Table 7-18	x38	R	x00	Descriptor 2 Status register
Table 7-22	x3C	R	x00	Descriptor 2 Pending Transfer register
Table 7-7	x40	R/W	x00	Descriptor 3 source memory start address
Table 7-11	x44	R/W	x00	Descriptor 3 destination memory start address
Table 7-15	x48	R/W	x00	Descriptor 3 Control register
Table 7-19	x4C	R	x00	Descriptor 3 Status register
Table 7-23	x50	R	x00	Descriptor 3 Pending Transfer register
Table 7-24	x54	W	x00	HPDMA Interrupt Clear register
Table 7-25	x58	R	x01	HPDMA Debug register