7.5 SYSREG Control Register
In addition to the specific HPDMA registers, the registers provided in Table 7-26 also control the behavior of the HPDMA peripheral. For more information on each register and associated bits, see 21 System Register Block.
| Register Name | Register Type | Flash Write Protect | Reset Source | Description |
|---|---|---|---|---|
| 21.5.19 Software Reset Control Register | RW-P | Bit | SYSRESET_N | Bit 17 is used for HPDMA reset ’1’ – Reset HPDMA ’0’ – Release from HPDMA reset |
| 21.5.17 Master Weight Configuration Register 1 | RW-P | Register | SYSRESET_N | Bits 4:0 define round robin weight values for the HPDMA master. |