14.2.4.4 I²C Interrupts

There are three interrupt signals for each I²C peripheral (I2C_0_INT, I2C_0_SMBALERT, and I2C_0_SMBSUS). These signals are generated by MSS I2C_0 and are mapped to INTISR 4, INTISR 5, and INTISR 6 in the Cortex-M3 processor NVIC controller. The I2C_1_INT, I2C_1_SMBALERT, and I2C_1_SMBSUS signals are generated by MSS I2C_1 and are mapped to INTISR 7, INTISR 8, and INTISR 9 in the Cortex-M3 processor NVIC controller. All interrupts enable bits within the NVIC, INTISR 4 through INTISR 9, correspond to bit locations 4 through 9.

Enable SMBus interrupts (I2C_X_SMBALERT and I2C_X_SMBSUS) in the I²C peripheral by setting the appropriate bits in the SMBUS register and clears the appropriate bit in the SMBus register in the interrupt service routine to prevent a reassertion of the interrupt.

The I2C_X_INT, I2C_X_SMBALERT, and I2C_X_SMBSUS I²C interrupt signals can be monitored by the FPGA logic through the fabric interface interrupt controller (FIIC). See Table 22-1 for further details.