22.2.1 Architecture Overview

The following figure shows the interfacing of the FIIC with NVIC, MSS peripheral interrupts, and FPGA fabric. The FIIC receives 43 level-sensitive active-high interrupts from the MSS as inputs. These MSS peripheral interrupts are combined, in a predetermined fashion, into 16 M2F interrupts (MSS_INT_M2F [15:0]) routed to the fabric. There is also a pass-through M3_NMI non-maskable interrupt from the watchdog timer and COMM_BLK interrupt, COMM_BLK_INT.

Figure 22-2. Block Diagram for Fabric Interface Interrupt Controller

There are 16 circuits, as shown in the following figure. Each circuit corresponds to a row in the preceding figure. The dedicated interrupts coming from the MSS peripherals are always connected to the 16 M2F interrupt signals.

Figure 22-3. Combinational Circuit for Mapping MSS Interrupts to a MSS_INT_M2F

Every peripheral interrupt in the MSS except I2C_SMBALERT0, I2C_SMBSUS0, I2C_SMBALERT1, and I2C_SMBSUS1 has access to the FPGA fabric through the dedicated inputs of the FIIC.

Each fabric MSS_INT_M2F signal can be triggered from one of the two possible scenarios:

Dedicated interrupts
Multiplexed group of interrupts

The selection of the MSS interrupt to a specific MSS_INT_M2F signal and making it available to the FPGA Fabric is done in two stages:

Select the group of interrupts: It can be done by setting Select_Mode bit of the M2F Interrupt Mode Register.
Enable the MSS interrupts: It can be done by writing to the appropriate FIIC INTERRUPT_ENABLE0 and INTERRUPT_ENABLE1 interrupt enable registers.

Table 22-1. Interrupt Line Signal Distribution
M2F Interrupt Signal	Dedicated	Select Group 0	Select Group 1
MSS_INT_M2F[0]	SPIINT0	ENVM_INT0	HPD_XFR_ERR_INT
MSS_INT_M2F[1]	SPIINT1	ENVM_INT1	MSSDDR_PLL_LOCK_INT
MSS_INT_M2F[2]	I2C_INT0	USB_DMA_INT	SW_ERRORINTERRUPT
MSS_INT_M2F[3]	I2C_INT1	Reserved	DDRB_INTR
MSS_INT_M2F[4]	MMUART0_INTR	I2C_SMBALERT0	ECCINTR
MSS_INT_M2F[5]	MMUART1_INTR	I2C_SMBSUS0	CACHE_ERRINTR
MSS_INT_M2F[6]	MAC_INT	I2C_SMBALERT1	SOFTINTERRUPT
MSS_INT_M2F[7]	USB_MC_INT	I2C_SMBSUS1	COMM_BLK_INTR
MSS_INT_M2F[8]	PDMAINTERRUPT	HPD_XFR_ERR_INT	Reserved
MSS_INT_M2F[9]	HPD_XFR_CMP_INT	MSSDDR_PLL_LOCK_INT	Reserved
MSS_INT_M2F[10]	TIMER1_INTR	SW_ERRORINTERRUPT	Reserved
MSS_INT_M2F[11]	TIMER2_INTR	DDRB_INTR	MDDR_IO_CALIB_INT
MSS_INT_M2F[12]	CAN_INTR	ECCINTR	Reserved
MSS_INT_M2F[13]	RTC_WAKEUP_INTR	CACHE_ERRINTR	FAB_PLL_LOCK_INT
MSS_INT_M2F[14]	WDOGWAKEUPINT	SOFTINTERRUPT	FAB_PLL_LOCKLOST_INT
MSS_INT_M2F[15]	MSSDDR_PLL_LOCKLOST_INT	COMBLK_INTR	FIC64_INT

It is possible to overlay one interrupt signal with two interrupt sources. For example, enable a dedicated interrupt and a group 0/1 interrupt. User logic in the fabric is responsible for determining the actual source of the interrupt by reading the appropriate peripheral interrupt Status Registers and determining which interrupt has occurred. Interrupts In and Out of the FIIC are asynchronous.

All interrupts originating from MSS blocks and fed into the FIIC are active-high level sensitive signals. Once asserted, the interrupt remains asserted until the user logic clears the appropriate MSS peripheral interrupt clear register. MSS_INT_M2F interrupt signals are serviced by the FPGA fabric. The exceptions to this are the SMBALERT and SMBSUS interrupts from the I2C peripheral. When these are held asserted, they are cleared by the far end I2C device, after a firmware-initiated sequence of operations. WDOGTIMEOUTINT is always passed straight through the block as M3_NMI.

F2M interrupts from the fabric are connected to the Cortex-M3 processor NVIC. MSS_INT_F2M [15:0], the 16 F2M interrupts from user logic in the fabric, are routed directly to the Cortex-M3 processor NVIC. F2M interrupts are level sensitive active-high inputs.

Once asserted, user logic in the fabric must keep the interrupt asserted until it is cleared by the  Cortex-M3 processor firmware. The SmartFusion 2 SoC FPGA FIIC does not synchronize fabric sourced peripheral interrupts to the fabric clock or MSS clock.