The Cortex-M3 processor sets the ENS1 and AA bits of the Control register.
The I2C peripheral receives its own address and the
direction bit from master.
The I2C peripheral generates an interrupt request, Status
register = 0x60 (Table 14-10).
The Cortex-M3 processor prepares to receive the data and then clears the SI bit in
Control register.
The I2C
peripheral receives the next data byte and generates the interrupt request. The Status
register contains a value of 0x80 or 0x88, depending on the AA bit. See Table 14-10.
The transfer is continued according to the STATUS Register – Slave-Receiver Mode.
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