32.8.18 ADCON3

ADC Control Register 3
Name: ADCON3
Offset: 0x114

Bit 76543210 
  CALC[2:0]SOITMD[2:0] 
Access R/WR/WR/WR/W/HCR/WR/WR/W 
Reset 0000000 

Bits 6:4 – CALC[2:0] ADC Error Calculation Mode Select bits

See the table below for selection details.
Table 32-5. ADC Error Calculation Mode
CALC Action During First Precharge Stage Application

DSEN = 0

Single-Sample Mode

DSEN = 1

CVD Double-Sample Mode(1)
000 ADRES-ADPREV ADRES-ADPREV First derivative of single measurement(2)
Actual CVD result in CVD mode(2)
001 ADRES-ADSTPT (ADRES-ADPREV)-ADSTPT Actual result vs. setpoint
010 ADRES-ADFLTR (ADRES-ADPREV)-ADFLTR Actual result vs. averaged/filtered value
011 Reserved Reserved Reserved
100 ADPREV-ADFLTR ADPREV-ADFLTR First derivative of filtered value(3) (negative)
101 ADLFTR-ADSTPT ADFLTR-ADSTPT Average/filtered value vs. setpoint
110 Reserved Reserved Reserved
111 Reserved Reserved Reserved
Note:
  1. When PSIS = 0, the value of ADRES-ADPREV) is the value of (S2-S1) from the Computation Modes table.
  2. When PSIS = 0.
  3. When PSIS = 1.

Bit 3 – SOI ADC Stop-on-Interrupt bit

ValueNameDescription
1 CONT = 1 GO is cleared when the threshold conditions are met, otherwise the conversion is retriggered
0 CONT = 1 GO is not cleared by hardware, must be cleared by software to stop retriggers
x CONT = 0 This bit is not used

Bits 2:0 – TMD[2:0] Threshold Interrupt Mode Select bits

ValueDescription
111 Interrupt regardless of threshold test results
110 Interrupt if ERR > UTH
101 Interrupt if ERR ≤ UTH
100 Interrupt if ERR < LTH or ERR > UTH
011 Interrupt if ERR > LTH and ERR < UTH
010 Interrupt if ERR ≥ LTH
001 Interrupt if ERR < LTH
000 Never interrupt