29.3.6 PTG Step Delay Limit Register

Note:

These bits are read-only when the module is executing step commands.
The value read from these register bits depends on the PTGIVIS bit (PTGCON[8]). Refer to Control Register Access for more information.

Table 29-12. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	PTGSDLIM
Offset:	0x3514


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
	PTGSDLIM[15:8]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PTGSDLIM[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:0 – PTGSDLIM[15:0] PTG Step Delay Limit Register bits^(1,2)

This register holds a PTG step delay value representing the number of additional PTG clocks between the start of a step command and the completion of a step command.

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