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29.3.5 PTG Timer1 Limit
Register
Note:
These bits are read-only when
the module is executing step commands. The value read from these
register bits depends on the PTGIVIS bit (PTGCON[8]). Refer to Control Register Access Table 29-11. Register Bit Attribute Legend Symbol Description Symbol Description Symbol Description R Readable
bit HC Cleared by
Hardware (Gray
cell) Unimplemented W Writable
bit HS Set by
Hardware X Bit is unknown
at Reset C Write to
clear S Software
settable bit x Channel
number
Name: PTGT1LIM Offset: 0x3510
Bit 31 30 29 28 27 26 25 24 Access Reset
Bit 23 22 21 20 19 18 17 16 Access Reset
Bit 15 14 13 12 11 10 9 8 PTGT1LIM[15:8] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0 PTGT1LIM[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 0
Bits 15:0 – PTGT1LIM[15:0]
PTG Timer1 Limit Register bits(1,2) General purpose
Timer1 Limit register.
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