29.3.1 PTG Control Register

Note:

These bits are read-only when the module is executing step commands.
This bit is only used with the PTGCTRL 0b1010/0b1011 step command software trigger options. Refer to Wait for Software Trigger for more information.
The PTGSSEN bit may only be written during a debugging session. See Single-Step Mode for more information.
These bits apply to the PTGWHI and PTGWLO commands only.

Table 29-7. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	PTGCON
Offset:	0x3500


Bit	31	30	29	28	27	26	25	24
	Reserved[2:0]			PTGDIV[4:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	23	22	21	20	19	18	17	16
	PTGPWD[3:0]					PTGWDT[2:0]
Access	R/W	R/W	R/W	R/W		R/W	R/W	R/W
Reset	0	0	0	0		0	0	0


Bit	15	14	13	12	11	10	9	8
	ON	Reserved	SIDL	PTGTOGL		PTGSWT	PTGSSEN	PTGIVIS
Access	R/W	r	R/W	R/W		R/W/HC	R/W	R/W
Reset	0	0	0	0		0	0	0


Bit	7	6	5	4	3	2	1	0
	PTGSTRT	PTGWDTO	PTGBUSY				PTGITM[1:0]
Access	R/W/HC	R/W/HS	R/HS/HC				R/W	R/W
Reset	0	0	0				0	0

Bits 31:29 – Reserved[2:0] Reserved, maintain as 0.

Bits 28:24 – PTGDIV[4:0] PTG Module Clock Prescaler (Divider) bits⁽¹⁾

Value	Description
`11111`	Divide by 32
`11110`	Divide by 31
`...`
`00001`	Divide by 2
`00000`	Divide by 1

Bits 23:20 – PTGPWD[3:0] PTG Trigger Output Pulse-Width (in PTG clock cycles) bits⁽¹⁾

Value	Description
`1111`	All trigger outputs are 16 PTG clock cycles wide
`1110`	All trigger outputs are 15 PTG clock cycles wide
`...`
`0001`	All trigger outputs are 2 PTG clock cycles wide
`0000`	All trigger outputs are 1 PTG clock cycle wide

Bits 18:16 – PTGWDT[2:0] PTG Watchdog Timer Time-out Selection bits⁽¹⁾

Value	Description
`111`	Watchdog Timer will time-out after 512 PTG clocks
`110`	Watchdog Timer will time-out after 256 PTG clocks
`101`	Watchdog Timer will time-out after 128 PTG clocks
`100`	Watchdog Timer will time-out after 64 PTG clocks
`011`	Watchdog Timer will time-out after 32 PTG clocks
`010`	Watchdog Timer will time-out after 16 PTG clocks
`001`	Watchdog Timer will time-out after 8 PTG clocks
`000`	Watchdog Timer is disabled

Bit 15 – ON PTG Enable bit

Value	Description
`1`	PTG is enabled
`0`	PTG is disabled

Bit 14 – Reserved Must be written as ‘`0`’

Bit 13 – SIDL PTG Stop in Idle Mode bit

Value	Description
`1`	Halts PTG operation when device is Idle
`0`	PTG operation continues when device is Idle

Bit 12 – PTGTOGL PTG Toggle Trigger Output bit⁽¹⁾

Value	Description
`1`	Toggles state of TRIG output for each execution of `PTGTRIG`
`0`	Generates a single TRIG pulse for each execution of `PTGTRIG`

Bit 10 – PTGSWT PTG Software Trigger bit⁽²⁾

Value	Description
`1`	Asserts the PTG software trigger
`0`	Deasserts the PTG software trigger (Level-Sensitive mode)/cleared by hardware (Edge-Sensitive mode)

Bit 9 – PTGSSEN PTG Single-Step Enable bit⁽³⁾

If in Debug mode:

1 = Enables Single-Step mode

0 = Disables Single-Step mode

If not in Debug mode:

Writes have no effect; read as ‘0’.

Bit 8 – PTGIVIS PTG Internal Counter/Timer Visibility bit^(1,4)

Value	Description
`1`	Reading the PTGSDLIM, PTGCxLIM or PTGTxLIM registers returns the current values of their corresponding internal Counter/Timer registers (PTGSD, PTGCx and PTGTx)
`0`	Reading the PTGSDLIM, PTGCxLIM or PTGTxLIM registers returns the value of these Limit registers

Bit 7 – PTGSTRT PTG Start Sequencer bit⁽³⁾

If not in Single-Step mode:

1 = Starts to sequentially execute the commands

0 = Stops executing the commands

If in Single-Step mode:

1 = Executes the next step command, then halts the sequencer

0 = Manually halts the sequencer/execution of signal command has completed (cleared by hardware)

Bit 6 – PTGWDTO PTG Watchdog Timer Time-out Status bit⁽¹⁾

Value	Description
`1`	PTG Watchdog Timer has timed out
`0`	PTG Watchdog Timer has not timed out

Bit 5 – PTGBUSY PTG State Machine Busy bit

Value	Description
`1`	PTG is running on the selected clock source
`0`	PTG state machine is not running

Bits 1:0 – PTGITM[1:0] PTG Input Trigger Operation Selection bits^(1,4)

Value	Description
`11`	Single-level detect with step delay not executed on exit of command, regardless of the `PTGCTRL` command (Mode 3)
`10`	Single-level detect with step delay executed on exit of command (Mode 2)
`01`	Continuous edge detect with step delay not executed on exit of command, regardless of the `PTGCTRL` command (Mode 1)
`00`	Continuous edge detect with step delay executed on exit of command (Mode 0)

29.3.1 PTG Control Register

Bits 31:29 – Reserved[2:0] Reserved, maintain as 0.

Bits 28:24 – PTGDIV[4:0] PTG Module Clock Prescaler (Divider) bits(1)

Bits 23:20 – PTGPWD[3:0] PTG Trigger Output Pulse-Width (in PTG clock cycles) bits(1)

Bits 18:16 – PTGWDT[2:0] PTG Watchdog Timer Time-out Selection bits(1)

Bit 15 – ON PTG Enable bit

Bit 14 – Reserved Must be written as ‘0’

Bit 13 – SIDL PTG Stop in Idle Mode bit

Bit 12 – PTGTOGL PTG Toggle Trigger Output bit(1)

Bit 10 – PTGSWT PTG Software Trigger bit(2)

Bit 9 – PTGSSEN PTG Single-Step Enable bit(3)

Bit 8 – PTGIVIS PTG Internal Counter/Timer Visibility bit(1,4)

Bit 7 – PTGSTRT PTG Start Sequencer bit(3)

Bit 6 – PTGWDTO PTG Watchdog Timer Time-out Status bit(1)