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19.3.2 DAC Control 2 Register
Table 19-9. Register Bit Attribute Legend Symbol Description Symbol Description Symbol Description R Readable
bit HC Cleared by
Hardware (Gray
cell) Unimplemented W Writable
bit HS Set by
Hardware X Bit is unknown
at Reset C Write to
clear S Software
settable bit x Channel
number
Name: DACCTRL2 Offset: 0x1D44
Bit 31 30 29 28 27 26 25 24 SSTIME[9:8] Access R/W R/W Reset 0 0
Bit 23 22 21 20 19 18 17 16 SSTIME[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 1 0 0 0 1 0 1 0
Bit 15 14 13 12 11 10 9 8 TMODTIME[9:8] Access R/W R/W Reset 0 0
Bit 7 6 5 4 3 2 1 0 TMODTIME[7:0] Access R/W R/W R/W R/W R/W R/W R/W R/W Reset 0 0 0 0 0 0 0 1
Bits 25:16 – SSTIME[9:0] Time from Start of Transition Mode until
Steady-State Filter is Enabled bits
Bits 9:0 – TMODTIME[9:0] Transition Mode Duration bits
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