19.3.4 DACx Data Register

Table 19-11. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	DACxDAT
Offset:	0x1D4C, 0x1D5C, 0x1D6C


Bit	31	30	29	28	27	26	25	24
					DACDAT[11:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	23	22	21	20	19	18	17	16
	DACDAT[11:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
					DACLOW[11:0]
Access					R/W	R/W	R/W	R/W
Reset					0	0	0	0


Bit	7	6	5	4	3	2	1	0
	DACLOW[11:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 27:16 – DACDAT[11:0] DACx High Data bits

In Hysteretic mode, Slope Generator mode and Triangle mode, this register specifies the high data value and/or limit for the DACx module. Valid values are from 205 to 3890.

Bits 11:0 – DACLOW[11:0] DACx Low Data bits

See DAC output level. In Hysteretic mode, Slope Generator mode and Triangle mode, this register specifies the low data value and/or limit for the DACx module. Valid values are from 205 to 3890.