19.3.3 DACx Control Low Register

Table 19-10. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	DACxCON
Offset:	0x1D48, 0x1D58, 0x1D68


Bit	31	30	29	28	27	26	25	24
							TMCB[9:0]
Access							R/W	R/W
Reset							0	0


Bit	23	22	21	20	19	18	17	16
	TMCB[9:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	15	14	13	12	11	10	9	8
	DACEN	IRQM[1:0]		EXTUPD	UPDTMDIS	CBE	DACOE	FLTREN
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
	CMPSTAT	CMPPOL	INSEL[2:0]			HYSPOL	HYSSEL[1:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 25:16 – TMCB[9:0] DACx Leading-Edge Blanking bits

These register bits specify the blanking period for the comparator, following changes to the DAC output during Change-of-State (COS), for the input signal selected by the HCFSEL[3:0] bits in SLPxCONL.

Bit 15 – DACEN Individual DACx Module Enable bit

Value	Description
1	Enables DACx module
0	Disables DACx module to reduce power consumption; any pending Slope mode and/or underflow condition is cleared

Bits 14:13 – IRQM[1:0] Interrupt Mode select bits

Value	Description
11	Generates an interrupt on either a rising or falling edge detect
10	Generates an interrupt on a falling edge detect
01	Generates an interrupt on a rising edge detect
00	Interrupts are disabled

Bit 12 – EXTUPD External Triggered Data Updates

Value	Description
1	New DACDAT is transferred to the active DAC data register when the selecteddac_slope_start[14:1] signal specified by the SLPCON[x] SLPSTRT[3:0] is asserted.
0	New DACDAT is immediately transferred to the active DAC data register. This is known as an immediate update.

Bit 11 – UPDTMDIS Update Transition Mode Disable

Value	Description
1	The transition mode is disabled for DACDATA updates, the output voltage will be smoother, but the DAC may be slower in reaching the target voltage.
0	Transition mode is applied following DACDATA updates to reduce time to reach new specified DAC output voltage. DAC output voltage transient ripple may be introduced.

Bit 10 – CBE Comparator Blank Enable bit

Value	Description
1	Enables the analog comparator output to be blanked (gated off) during the recovery transition following the completion of a slope operation.
0	Disables the blanking signal to the analog comparator; therefore, the analog comparator output is always active.

Bit 9 – DACOE DAC Output Buffer Enable bit

Value	Description
1	DACx analog voltage is connected to the DACOUTx pin
0	DACx analog voltage is not connected to the DACOUTx pin

Bit 8 – FLTREN Comparator Digital Filter Enable bit

Value	Description
1	Digital filter is enabled
0	Digital filter is disabled

Bit 7 – CMPSTAT Comparator Status bits

Current state of comparator output including CMPPOL selection

Bit 6 – CMPPOL Comparator Output Polarity Control bit

Value	Description
1	Output is inverted
0	Output is noninverted

Bits 5:3 – INSEL[2:0] Comparator Input Source Select bits

Value	Description
111	Reserved
110	Reserved
101	Reserved
100	Reserved
011	CMPxD input pin
010	CMPxC input pin
001	CMPxB input pin
000	CMPxA input pin

Bit 2 – HYSPOL Comparator Hysteresis Polarity Select bit

Value	Description
1	Hysteresis is applied to falling edge of comparator output
0	Hysteresis is applied to rising edge of comparator output

Bits 1:0 – HYSSEL[1:0] Comparator Hysteresis Select bits

Value	Description
11	45 mV hysteresis
10	30 mV hysteresis
01	15 mV hysteresis
00	No hysteresis selected