19.3.1 DAC Control 1 Register

Note:

These bits should only be changed when DACON = 0 to avoid unpredictable behavior.

Table 19-8. Register Bit Attribute Legend
Symbol	Description	Symbol	Description	Symbol	Description
R	Readable bit	HC	Cleared by Hardware	(Gray cell)	Unimplemented
W	Writable bit	HS	Set by Hardware	X	Bit is unknown at Reset
C	Write to clear	S	Software settable bit	x	Channel number

Name:	DACCTRL1
Offset:	0x1D40


Bit	31	30	29	28	27	26	25	24
	RREN		POSINLADJ[5:0]
Access	R/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset	0		1	1	1	1	1	1


Bit	23	22	21	20	19	18	17	16
		NEGINLADJ[6:0]
Access		R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset		1	1	1	1	1	1	1


Bit	15	14	13	12	11	10	9	8
	DACON		DACSIDL	DNLADJ[4:0]
Access	R/W		R/W	R/W	R/W	R/W	R/W	R/W
Reset	0		0	0	0	0	0	0


Bit	7	6	5	4	3	2	1	0
		Reserved				FCLKDIV[2:0]
Access						R/W	R/W	R/W
Reset		0				0	0	0

Bit 31 – RREN Ripple Reduction Enable

Value	Description
1	Ripple Reduction mode is enabled
0	Ripple Reduction mode is disabled

Bits 29:24 – POSINLADJ[5:0] Positive INL Correction value

The number of ones in this register controls the rise time of the PDM drivers. Reducing the number of ones in this register will increase the rise time. This bit field only exists if a TYPE#2 filter is instantiated. This value is shared by all of the PDM DACs.

Bits 22:16 – NEGINLADJ[6:0] The number of ones in this register controls the fall time of the PDM drivers. Reducing the number of ones in this register will increase driver fall time. This bit field only exists if a type #2 filter is instantiated. This value is shared by all of the PDM DACs.

The number of ones in this register control the rise time of the PDM drivers. Reducing the number of ones in this register increase the rise time. This bit field only exists if a TYPE#2 filter is instantiated. This value is shared by all of the PDM DACs.

Bit 15 – DACON Common DAC Module Enable bit

Value	Description
1	Enables DAC modules
0	Disables DAC modules and disables FSCM clocks to reduce power consumption; any pending Slope mode and/or underflow condition is cleared

Bit 13 – DACSIDL DAC Stop in Idle Mode bit

Value	Description
1	Discontinues module operation when device enters Idle mode
0	Continues module operation in Idle mode

Bits 12:8 – DNLADJ[4:0] DNL Adjustment Override

Each bit assert to a “1”overrides the DNL pulse stretcher finger control. Each “1” reduces the amount of DNL pulse stretching, thus reducing the amount of DNL correction. This bit field only exists if a type #2 filter is instantiated. This value is shared by all of the PDM DACs

Bit 6 – Reserved

Bits 2:0 – FCLKDIV[2:0] Comparator Filter Clock Divider bits

Value	Description
111	Divide-by-8
110	Divide-by-7
101	Divide-by-6
100	Divide-by-5
011	Divide-by-4
010	Divide-by-3
001	Divide-by-2
000	1x