27.4.4.3 Dual Edge Buffered Compare (PWM) Mode

When MOD[3:0] = 0101, the module functions the same as in Dual Edge Compare mode, with the exception that CCPxRA and CCPxRB are double-buffered. In all other respects of output signal generation, operation is the same. Writes to the Data registers (CCPxRA and CCPxRB) are stored in holding buffers. The contents of the buffers are transferred to CCPxRA and CCPxRB on a Time Base Reset.

Dual Edge Buffered Compare mode is only available in 16-bit mode. The T32 bit has no affect.

Dual Edge Buffered Compare mode uses these Timer/Data registers:
  • CCPxTMRL as the Timer register
  • CCPxRA for the Rising Edge Value register of the next period
  • CCPxRB for the Falling Edge Value register of the next period
  • CCPxPRL for the Timer Period register

The Dual Edge Buffered Compare mode is used to create PWM signals. The buffering of the CCPxRA and CCPxRB registers allows the user to create glitch-free updates to the PWM signal edge times.

If edge-aligned PWM signals are desired, maintain CCPxRA with a value of 0000h. Using a non-zero value for CCPxRA creates PWM signals with arbitrary phase alignments.

CCPxRA and CCPxRB are double-buffered. Data are written from the buffers to CCPxRA and CCPxRB under these conditions:
  • When the timer is reset to 0000h on a Sync event (source selected by SYNC[4:0] is asserted)
  • When the timer rolls over from FFFFh to 0000h
  • When the module is disabled (CCPON = 0); any writes to CCPxRA and CCPxRB are immediately transferred to their Compare registers

Figure 27-20 shows the timing for writing to the buffer in Sync operation. CCPxRA and its buffer are shown; CCPxRB and its buffer operate in an identical manner. For output signal generation, refer to Dual Edge Compare Mode.

The procedure for configuring the module for Dual Edge Buffered Compare mode is shown in Setup for Dual Edge Buffered Compare Mode.

Figure 27-20. Buffer Writes in Dual Edge Buffered Compare Mode

Setup for Dual Edge Buffered Compare Mode

// Set CCP operating mode
CCP1CON1bits.CCSEL = 0;         // Set SCCP operating mode (OC mode)
CCP1CON1bits.MOD = 0b0101;      // Set mode (Buffered Dual-Compare/PWM mode)
//Configure SCCP Timebase
CCP1CON1bits.T32 = 0;           // Set timebase width (16-bit)
CCP1CON1bits.TMRSYNC = 0;       // Set timebase synchronization (Synchronized)
CCP1CON1bits.CLKSEL = 0b000;    // Set the clock source (Tcy)
CCP1CON1bits.TMRPS = 0b00;      // Set the clock pre-scaler (1:1)
CCP1CON1bits.TRIGEN = 0;        // Set Sync/Triggered mode (Synchronous)
CCP1CON1bits.SYNC = 0b00000;    // Select Sync/Trigger source (Self-sync)
//Configure SCCP output for PWM signal
CCP1CON2bits.OCAEN = 1;         // Enable desired output signals (OC1A)
CCP1CON3bits.OUTM = 0b000;      // Set advanced output modes (Standard output)
CCP1CON3bits.POLACE = 0;        // Configure output polarity (Active High)
CCP1TMR = 0x0000;               // Initialize timer prior to enable module.
CCP1PR = 0x0000FFFF;            // Configure timebase period
CCP1RA = 0x00001000;            // Set the rising edge compare value
CCP1RB = 0x00008000;            // Set the falling edge compare value
CCP1CON1bits.CCPON = 1;         // Turn on SCCP module