27.4.4.2 Dual Edge Compare Mode

When MOD[3:0] = 0100, the Output Compare channel is configured to produce a continuous series of pulses. The parameters for the pulse train are determined by the CCPxRA, CCPxRB and CCPxPRL.

Dual Edge Compare mode is only available in 16-bit mode. The T32 bit has no affect.

Dual Edge Compare mode uses these timer/data registers:

CCPxTMRL as the Timer register
CCPxRA for the Rising Edge Value register
CCPxRB for the Falling Edge Value register
CCPxPRL for the Timer Period register

Figure 27-14 depicts the signal timing for Dual Edge Compare mode. The typical operation in this mode is as follows:

When Dual Edge Compare mode is enabled, the pin state is driven low. At some point, the timer is enabled (triggered) by a hardware or software event to start the count process.
Upon the first timer compare match with the Compare register, CCPxRA, the output pin will be driven high.
When the incrementing timer count matches the Compare register, CCPxRB, the second and trailing edge (high-to-low) of the pulse is driven onto the output pin. At this second compare, the Output Compare Interrupt Flag (CCPxIF) is generated.
The Timer Interrupt Flag (CCTxIF) is generated, along with the CCP Sync signal, when the timer rolls over (when SYNC[4:0] = 00000) or when an event is defined by SYNC[4:0].
The output pulses continue repeatedly until the mode is terminated by the application or a device Reset occurs.

This is the prototype case, where the Timer Period and the Match registers are all different values, ordered as (Timer Period > CCPxRB > CCPxRA). There are special cases, however, where the conditions differ, resulting in a specific type of output. The cases are listed in Table 27-16, and are described in the following sections.

Figure 27-14. Typical Dual Edge Compare Timing Sequence

Table 27-16. Special Conditions for Dual Edge Compare Operations
Condition	Output	Output Compare Interrupt on Falling Edge of OCx Pin	Timer Interrupt When Timer Matches Period
CCPxRA = CCPxRB	No output, OCx pin remains low	None	Yes
CCPxRA = CCPxRB + 1	One pulse	Yes	Yes
Timer Period < CCPxRA⁽¹⁾	No output	N/A⁽²⁾	Yes
Timer Period = CCPxRB⁽¹⁾	OCx goes low at CCPxRB	Yes	Yes
Timer Period < CCPxRB⁽¹⁾	Continuous high	None	Yes
Timer Period = CCPxRB, CCPxRA = `0`⁽¹⁾	CCP goes high when TMR = `1` and goes low when CCPxRB matches timer	Yes	Yes
CCPxRA > CCPxRB	Pulse train	Yes	Yes
Note: Timer period is either the period register value or when the timer is reset by the input selected by SYNC[4:0]. If CCPxRB is also less than the timer period, an interrupt will be generated, even though there is no activity on the OCx pin.