6.6.1 Features

• Comprehensive IEEE 754-2008/2019 Compliant Instruction Set
  • Supports both Single and Double Precision operations for most instructions
  • Supports all required rounding modes
• Closely Coupled to PIC32A CPU Core
  • Instructions issued from CPU core as part of application instruction stream
  • Independent instruction pipeline and hazard management
• 32 x 32-Bit Data Registers (F-Regs)
  • May be used to hold 32-bit Single Precision or 64-bit Double Precision values
  • Base plus 7 partial FPU register contexts
• Optional Subnormal Handling for Improved Performance
  • Subnormal result “Flush-To-Zero” (FTZ) mode
  • Subnormal operand “Subnormals-Are-Zero” (SAZ) mode
• Comprehensive Exception Implementation and Reporting Structure
  • IEEE 754-2019 compliant exception implementation
  • Additional exceptions supported for Huge Integer results and Subnormal operands
• Debug Features Supported:
  • Exception address capture register (FEAR)
  • Exception break signaling
  • NaN propagation