6.6.5 Floating-Point Control Register(1)

Note:
  1. The FCR register is not memory mapped.
  2. Floating-Point Exception Mask bits, FCR [6:0]: Each Exception Mask bit corresponds to an Exception Status flag in the FSR. The Mask bit must be clear to allow the exception event to generate an interrupt to the CPU. The Underflow Mask bit (FCR.UDFM) is also used as part of the Flush-to-Zero (FTZ) mode enable as discussed in Flush-To-Zero (FTZ).

    Floating-point rounding mode control, FCR [9:8]: These bits define the global IEEE 754 compatible rounding mode used by the FPU instruction.

    Floating-point subnormal override mode control, FCR [11:10]: These bits enable the Subnormals-Are-Zero (SAZ) and Flush-to-Zero (FTZ) subnormal override modes supported by the FPU.

Table 6-41. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Gray cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
CWrite to clearSSoftware settable bitxChannel number
Name: FCR

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
     SAZFTZRND [1:0] 
Access R/WR/WR/WR/W 
Reset 0000 
Bit 76543210 
  SUBOM HUGIM INXM UDFM OVFMDIV0MINVALM 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0000000 

Bit 11 – SAZ Subnormals Are Zero Operand Mode bit

ValueDescription
1Subnormals Are Zero mode is enabled
0Subnormals Are Zero mode is disabled

Bit 10 – FTZ Flush To Zero Result Mode bit

ValueDescription
1Flush To Zero mode is enabled
0Flush To Zero mode is disabled

Bits 9:8 – RND [1:0] FPU Rounding Mode bit

ValueDescription
11IEEE Round to Negative Infinity (floor)
10IEEE Round to Positive Infinity (ceiling)
01IEEE Round to Zero (truncate)
00IEEE Round to Nearest (even)

Bit 6 – SUBOM  Subnormal Operand Exception Mask bit

ValueDescription
1Subnormal exception is masked
0Subnormal exception is not masked

Bit 5 – HUGIM  Huge Integer Exception Mask bit

ValueDescription
1Huge Integer exception is masked
0Huge Integer exception is not masked

Bit 4 – INXM  Inexact Exception Mask bit

ValueDescription
1Inexact exception is masked
0Inexact exception is not masked

Bit 3 – UDFM  Underflow Exception Mask bit

ValueDescription
1Underflow exception is masked
0Underflow exception is not masked

Bit 2 – OVFM Overflow Exception Mask bit

ValueDescription
1Overflow exception is masked
0Overflow exception is not masked

Bit 1 – DIV0M Divide By Zero Exception Mask bit

ValueDescription
1Divide By Zero exception is masked
0Divide By Zero exception is not masked

Bit 0 – INVALM Invalid Exception Mask bit

ValueDescription
1Invalid exception is masked
0Invalid exception is not masked